DE3831530A1 - Data processing circuit to process data with different bit lengths - Google Patents

Abstract

Traditional data processing circuits give problems in processing data with different bit lengths. The data processing system with a memory device has even-numbered addresses and odd-numbered addresses. In both long data bit mode and short data bit mode, an even-numbered address and an odd-numbered address are accessed. The data processing system has a circuit (200) to carry out the data communication with an odd-numbered address via an upper data bus (6) or a lower data bus (5) in short data bit mode, and a circuit (150) to carry out the data communication with an odd-numbered address via the lower data bus (5) in both long and short data bit modes. Because of this construction, data communication via the lower data bus only, for both even-numbered and odd-numbered addresses, is made possible in short data mode. This data processing system can be used, for example, in a microcomputer. <IMAGE>

Description

The invention relates generally to a data processing circuit for selectively processing data in two different byte lengths, and in particular to a memory system to which both 2 ⁿ bits ( n is an integer) and 2 ^m bits ( m is an integer and fulfills the Condition m ≦ λτ n ) can be accessed.

With the development of the microcomputer, the data width of 4 bit to 8 bit and increased from 8 bit to 16 bit. In particular are 16-bit microcomputers in such industrial and user areas widespread, where mainly 8 bit Microcomputers are used due to strong demand after higher performance. Generally is in one Microcomputer an EPROM (electrically programmable write-only Memory) for storing a suitable one for the respective application User program provided, usually an EPROM with 8 bit structure is used.

Fig. 1 shows a system example with an 8-bit EPROM and a 16 bit CPU. According to Fig. 1, the system includes a 16-bit CPU (central processing unit) 1 such as M37790 by Mitsubishi Denki Kabushiki Kaisha, Tokyo, Japan, two 8-bit EPROM 2 and 3, that is, an EPROM 2 for even addresses (less significant Addresses) and an EPROM 3 for odd-numbered addresses (more significant addresses). For example, each EPROM is a product number 27128 from Mitsubishi Denki Kabushiki Kaisha, Tokyo, Japan.

The CPU 1 has an address connection 51 for outputting 15 bit address signals A 0 to A 14 , an input / output connection 52 for the lower (less significant) 8 bit data D 0 to D 7 , an input / output Port 54 for input and output of the upper (more significant) 8-bit data and a BHE port 53 for output of a signal, ie a byte high enable signal, which indicates access to the upper data of the odd-numbered addresses.

The EPROM 2 for the even-numbered addresses has an address input connection 61 for receiving 14 bit address signals A 1 to A 14 from the 15 bit address signals A 0 to A 14 from the CPU 1 , an output enable connection 62 for receiving the am least significant address signal A 0 from the CPU 1 , a data output port 63 for outputting 8 bit data D 0 to D 7 and a chip enable port 64 connected to ground. Since the EPROM 2 has its chip release connection 64 connected to ground, this is always in the active state (release state). When an "L" signal is applied to the output enable terminal 62 , the EPROM 2 is enabled to output data stored in an address corresponding to the selected address input terminal 61 from the terminal 63 .

The odd address EPROM 3 has an address input terminal 71 for receiving 14 bit address signals A 1 to A 14 from the CPU 1 , an output enable terminal 72 for receiving the odd address selection signal from the CPU 1 , and a data output terminal 73 for outputting 8 bit data D 0 to D 7 in addresses corresponding to the address signals applied to the address input terminal 71 and a chip enable terminal 74 connected to ground potential. Since the chip enable connection 74 is connected to ground potential, the EPROM 3 is always in the "enable" state. When the byte high enable signal (odd address select signal), since it is applied to the output enable terminal 72 , is "L", the EPROM 3 becomes the output of the contents of the addresses through the to the address input terminal 71 applied address signals A 1 to A 14 are determined, activated by the data output terminal 73 .

The 15 bit address signals A 0 to A 14 from the CPU 1 are sent on a 15 bit address bus 4 . The 8 bit data D 0 to D 7 from the EPROM 2 are applied to the lower data input / output connection 52 of the CPU 1 via a lower 8 bit data bus 5 . The 8 bit data from the EPROM 3 is applied to the upper 8 bit data input / output port 54 of the CPU 1 via an upper 8 bit data bus 6 .

The selection of the even-numbered address and the odd-numbered address is carried out by the least significant address signal A 0 . That is, when the address signal A 0 is "0"("L"), an even-numbered address is selected, and when the least significant address signal A 0 is "1"("H"), an odd-numbered address is selected.

If the byte high enable signal is "L", it determines one Access to an odd address if it's "H", it prevents access to an odd address.

Fig. 2 shows in a timing diagram the write cycle of the data in a structure with 16 bit CPU and 8 bit EPROM. The cycle will now be described with reference to FIGS. 1 and 2.

Most CPUs with a 16 bit data bus can access consecutive even addresses and odd addresses for the two EPROMs 2 and 3 in the same CPU cycle. The following is the description of the mode of operation in which the CPU 1 accesses the EPROMs 2 and 3 in 16 bits. First, even-numbered address signals A 0 to A 14 appear on the address bus 4 . In particular, the least significant address signal A 0 is at "L" level. Therefore, the signal is set to "L" level and the address signals applied to the address bus 4 are drawn into the EPROMs 2 and 3 , respectively. The least significant address signal A 0 is applied to the output enable terminal 62 of the EPROM 2 for the even addresses, while the signal is applied to the output enable terminal 72 of the EPROM 3 for the odd addresses. Therefore, both EPROMs 2 and 3 simultaneously go into the output enable state for the output of data in addresses which are determined by the address signals A 1 to A 14 . Since the address signals A 1 to A 14 belong to both EPROMs 2 and 3 , the data output by both EPROMs 2 and 3 become continuous 2-byte data which have an even-numbered address and a subsequent odd-numbered address. The data from the EPROM 2 for the even-numbered addresses are applied to the lower data bus 5 via the data output terminal 63 , while the 8-bit data from the EPROM 3 for the odd-numbered addresses are applied from the data output terminal 73 to the upper data bus 6 . The CPU 1 receives the continuous 2-byte data simultaneously via the lower data bus 5 and the upper data bus 6 . The CPU 1 repeats the above-described operation of reading the 16-bit data from the EPROMs 2 and 3 if necessary in view of the content to be processed.

Depending on the content to be processed, the CPU sometimes only needs the data in byte format (8 bits). In this case, only one of the least significant signal A 0 and the signal is activated for access to EPROM 2 or 3 ("L" level). To access odd-numbered addresses in EPROM 3 , the least significant address signal A 0 is set to "1"("H") and the signal is set to "L". For this reason, an "H" signal is applied to the output enable terminal 62 of the EPROM 2 for the even-numbered addresses, so that the EPROM 2 goes into the output disabled state. Since an "L" signal is applied to the output enable terminal 72 of the EPROM 3 for the odd-numbered addresses, the EPROM 3 now goes into the output enable state, whereby there is 8 bit data in an address which corresponds to the from the CPU 1 applied address signals A 1 to A 14 , outputs to the upper data bus 6 . As a result, 8-bit data is read from the odd-numbered addresses.

For the access of the EPROM 2 to only the even-numbered addresses, the least significant address signal A 0 is set to "0"("L" level) and the signal is set to "H". Therefore, the EPROM 3 goes into the output disable state for the odd-numbered addresses, while the EPROM 2 goes into the output enable state for the even-numbered addresses, the EPROM 2 8-bit data into addresses which are via the address bus 4 applied address signals A 1 to A 14 correspond to the lower data bus 5 outputs.

In both modes, namely access in units of 8 bits or access in units of 16 bits, the data stored in an odd address appear on the lower data bus 5 , while the data stored in an even address appear on the upper data bus 6 .

Instead of the two 8-bit EPROMs described above, the system can contain a 16 bit EPROM.

Figure 3 shows a connection between the CPU and the EPROM in a system using a 16 bit EPROM.

ToFig. 3 has the 16 bit CPU1 an address output port 55 for the output of 15 bit address signalsA 0 toA 14, a Data input / output connector56 for entering and outputting the lower 8 bit dataD 0 toD 8th, a data input / output Connection57 for input and output of the upper 8 bitsD 8th toD 15, a release port58 to issue a release signal   to activate the memory and a connector59 for output of the read / write signalR/ which is the read / write operation of memory determined on.  

The 16 bit EPROM2nd a has an address input port65 to the Receive 14 bit address signalsA 1 toA 14, the data output connector 66 to output the lower 8-bit dataD 0 toD 7, a data output port67 to output the upper 8 bit data D 8th toD 15, a chip release connector68 to receive one Release signals  from the CPU1 and an exit release Connection69 for inverting and receiving reading / writing SignalsR/  from the CPU1 on. If at the chip release- Connection68 an "L" signal is applied, the EPROM occurs2nd a in the release state, and if a to the output release Connection69 an "L" signal is applied, it goes into the output Release status.

FIG. 4 is a timing chart showing the write cycle of a case in which the 16-bit word EPROM shown in FIG. 3 is used. The write cycle with a 16 bit EPROM will be explained with reference to FIGS. 3 and 4.

Address signalsA 0 toA 14 are from the CPU1 on the address bus 4th filed. Then the release signal falls  from the CPU1 off, so that the EPROM2nd a enters the release state, being the 14th Bit address signalsA 1 toA 14 on the address bus4th takes over and Data in addresses that correspond to the address signals applied, issues. At this point is the read / write signalR/  For the reading operation to "H" and an "L" signal is sent to the output Release connection69 created. Hence the EPROM2nd a in the Output enable state and the 16 bit data contained in addresses are stored, the applied address signalsA 1 toA 14  correspond to the data buses5 and6 transfer. The CPU1 receives through a lower 8 bit data input connector 50 on the data bus5 read out lower 8 bit data. Meanwhile become the top 8 bit dataD 8th toD 15 over the top Data bus6 to the upper data input connector57 the CPU1  created. At this point the EPROM sends2nd a the content of the  Address of the address signals createdA 1 toA 14 correspond, off, so that an 8 bit information in an even number Address and an 8 bit information in the odd number Address that follows the accessed even number address, can be read out simultaneously.

In a structure other than the structure described above that uses an EPROM, the CPU has a random access memory (RAM) or the like for storing data. In this case, 16-bit random access memory is used. This random access memory (RAM) has even-numbered addresses and odd-numbered addresses for storing data in byte size, the word-size (16-bit) data consisting of data from successive even-numbered and odd-numbered address data. In this case, the data of the even-numbered address is also output on the lower 8-bit data bus, while the data of the odd-numbered address are output on the upper 8-bit data bus. This should be understood to mean that the EPROM of FIG. 3 is simply replaced by the RAM.

Fig. 5 shows a relationship between the address and data buses when an 8-bit memory or 16-bit memory is connected to a CPU with a 16-bit data bus. As can be seen from FIG. 5, both in the 8-bit memory and in the 16-bit memory, the address is selected by address signals A 1 to A 14 , so that the address N ( N is an integer) and the address N + 1 is accessed simultaneously. Specifically, an even-numbered address and the subsequent odd-numbered address are selected by the address signals A 1 to A 14 . At this time, the even address data appears on the lower data bus, while the even address data appears on the upper data bus.

In general, a CPU has a register for storing data, a program, or the like. In the case of the registers in a CPU, the registers connected to the upper data bus and the registers connected to the lower data bus are fixed. Namely, as shown in Fig. 6, register B is connected to the upper data bus and thus to the odd address of the memory, while register A is connected to the even address through the lower data bus. This structure poses some problems, which are described below. Depending on the work content of the CPU, there is a case in which only upper 8 bit data are required and not the lower 8 bits. In other words, there is a case where only 8 bit data of the odd address is required. In this case, since the CPU is generally designed to access register A earlier, the contents of register B should be transferred to register A once for reading. In this case, a register exchange instruction such as "XCH" is prepared for exchanging the contents of register B and register A. When the content of the register B is transferred to the register A , the transfer of the content takes place in a conventional structure by bitwise shifting. Therefore, the exchange takes a lot of time, and therefore another problem arises that the desired arithmetic processes and data processes are not carried out at high speed. In particular, when a particular process is desired that uses only 8-bit data of the odd-numbered address, the 8-bit data is always stored in the upper register B , so that the data should be transferred to register A at once. As a result, the process using odd address data cannot be performed at high speed. This problem is described in more detail below with reference to FIGS. 7 to 9. A case will now be discussed in which a particular workflow is performed on each of the 8-bit data stored in two 8-bit memories, the resulting data again being stored in original storage locations in a storage system shown in FIG 16 bit CPU can be saved. According to FIG. 7, the memory system includes a 16-bit CPU 500, a memory 510 for storing 8-bit data of an odd-numbered address, and a memory 520 for storing 8-bit data of an even-numbered address. The memory 510 is connected to an upper byte data bus DBH via an 8 bit data bus 511 . The memory 520 is connected to a lower data bus DBL via an 8 bit data bus 512 . The 16-bit CPU 500 receives and transmits data from odd-numbered addresses from / to the data bus DBH and data from even-numbered addresses from / to the data bus DBL . The memory map or the memory locations of the memory system according to FIG. 7 are shown in FIG. 8. As an example, a program used in this process is shown in Fig. 9A. FIG. 9B denotes the meaning of each step of the program, and FIG. 9C shows the content in a 16-bit register A , which is provided in the CPU 500 after the corresponding program step has been completed. The differences between the 16-bit register A and the 8-bit register A shown in FIG. 6 should be noted.

When the CPU processes the workflow with 8 bit data, it first accesses both memories 510 and 520 and loads the accessed 16 bit data into the 16 bit register A with the data of the odd address and the data of the even address, which are stored in the upper 8 bit positions and lower 8 bit positions in register A. Then the CPU 500 processes lower byte data in order to achieve a result, since only lower byte data in register A can be processed in the 8-bit workflow. A byte exchange is performed and the contents of register A are stored once in the original locations of memories 510 and 520 . Again, the cycle described above for storing result a (first result) and result b (second result) is performed in the original locations of the respective memories 510 and 520 . As shown in detail in Figs. 9A to 9C, the byte exchange command "RLA # 8" is executed several times. This byte exchange is carried out by shifting the data bit by bit into register A , which takes a lot of time. If the program is in the form of a loop, the time required for the byte exchange is also added up, which prevents the program from being carried out quickly.

Furthermore, there is the further problem that the contents of the 8-bit register A (or lower byte register) do not appear in odd-numbered addresses, e.g. B. can be stored in the upper byte data memory.

If a 16-bit EPROM consists of two EPROMs and can only process 8-bit data, EPROMs must also be used in pairs for the even-numbered address and for the odd-numbered address. In this case, if an incorrect EPROM is used for the pair, or the position of the pair of EPROMs is reversed during assembly, the data stored in the EPROM pair will have no order. As a result, the address signals generated by the CPU do not match the stored content, so that the system including the CPU and the memory do not operate correctly. The reason for this is that an 8-bit PROM writer is usually used for programming the 8-bit EPROM, the programming of the EPROMs being carried out one by one, so that the program for the even-numbered addresses and the program for the odd-numbered ones Addresses should be carried out separately in the two EPROMs. Furthermore, in a multiple CPU system with additional 8-bit CPUs 600 coupled to the lower byte data bus DBL as shown in FIG. 10, the 8-bit CPU 600 cannot store 8-bit data from odd-numbered addresses access the memory. Referring to Fig. 11, which illustrates the memory map for the multiple CPU system of Fig. 10, this means that the 8-bit CPU 600 does any processing of data from odd-numbered addresses N + i ( N = 2 n , i = 1, 2,...), As shown by the hatched areas in FIG. 11, which reduces the performance of a multiple CPU system with at least one CPU that processes data with different bit lengths.

The object of the invention is to eliminate the disadvantages of the conventional data processing system described above and to provide an improved data processing circuit which can process 2 ⁿ -bit data and 2 ^m -bit data, where m < n , a data processing system for programming an odd number and one To provide an even-numbered address in an EPROM, to provide a memory circuit with a data flow controller that allows access to data in 2 ⁿ bits and 2 ^m bits, where m and n are integers that satisfy the condition m ≦ λτ n , an improved method for processing data in 2 ⁿ bits and 2 ^m bits, and to provide a 16 bit EPROM that can be programmed with a conventional 8 bit PROM recorder.

The data processing system according to this invention has a memory device which enables access of at least 2 ⁿ bits, and 2 ^m ( m ≦ λτ n ) first data input / output connections, 2 ^m second data input / output connections for receiving and transmitting data from and having to the CPU, and elements lower in response to the Datenbitlängensignal, upper data strobe signal and the upper / address selection signal if the Datenbitlängensignal 2 determines ⁿ bits, selectively the corresponding 2 ⁿ first data input / output terminals with the lower 2 ⁿ bit of the second Data input / output connectors connects.

In the structure described above, if the data bit length signal the 2 ^m  Bit determines the 2nd ^m  or 2nd ⁿ  first data input / - output connections with the 2nd ^m  or corresponding second Data input / output connector corresponding to the upper data enable signal  and the upper / lower address selection signal connected, and if the data bit length signal 2 ⁿ  Bit determines is determined by the address signal 2 ⁿ  Bit first data input / Output connection with the bottom 2 ⁿ  Bit input / output connection of the second input / output connections. Therefore appear when accessed in 2 ⁿ  Only selectively bits the data on the lower 2nd ⁿ Bit of second data input / output connection. As a result, it can operate at high speed be done without sharing the contents of the top and lower registers of the CPU, whereby the one in the 8th Bit CPU used memory can be used in the 16 bit CPU can, the data material used in the 8 bit CPU in the 16th Bit CPU can be used, as well as one originally used for programming of an 8 bit EPROM used PROM recorder for programming of memory can be used, which means that a 16 bit Computer system constructed using the prior art can be.

These and other features and advantages of the invention result from the description of exemplary embodiments based on the figures.

Fig. 1 shows an example of a system structure with a 16 bit CPU with 8 bit EPROMs;

FIG. 2 shows the time course of the write cycle of the memory system shown in FIG. 1;

Figure 3 shows an example of a connection in a computer system having a 16 bit CPU and a 16 bit EPROM;

Fig. 4 shows the time course of the read cycle when using a 16-bit EPROM;

Fig. 5 shows the corresponding relationship between the memory address and the data bus in a 16 bit memory system;

Fig. 6 shows the corresponding relationship between the memory address and the registers in the CPU in a 16-bit CPU;

Fig. 7 schematically shows a storage system;

Figure 8 shows a memory map for the system of Figure 7;

FIG. 9A to 9C show an example of a program for processing 8-bit data in a 16-bit CPU system of FIG. 7;

Fig. 10 schematically shows a multi-CPU system having an 8-bit CPU and a 16-bit CPU;

Fig. 11 shows a memory map of the multiple CPU system of Fig. 10;

Fig. 12 shows an example of an embodiment of a structure of a memory element according to this invention;

Fig. 13 shows the relationship between the modes and the voltages applied to the terminals of the memory shown in Fig. 12;

Fig. 14 shows another structure of a byte signal generating circuit used in the structure of Fig. 12;

Fig. 15 shows the connecting structure between the 16-bit CPU and a 16 bit memory element with the 16 bit bus;

Fig. 16 shows the timing of reading / writing of data in the system structure shown in Fig. 15;

Fig. 17 shows the connection setup between the CPU and the memory element using the 16 bit memory element with the 8 bit bus;

Fig. 18 shows the waveforms illustrating the reading / writing of data in the structure shown in Fig. 17;

Fig. 19 shows the relationship between the memory address and the data bus with the 16 bit bus;

Fig. 20 shows the relationship between the memory address and the data bus with the 8-bit bus;

Fig. 21 and 22 show the corresponding relationship between the memory address and the registers in the CPU with the 8-bit bus;

FIG. 23 schematically shows a storage system according to an embodiment of this invention;

Figure 24 shows a memory map of the system of Figure 23;

Fig. 25A shows an example of a program for processing 8-bit data in the 16-bit CPU system of Fig. 23;

Figure 25B shows the flow of data at each step in the program of Figure 25A;

Fig. 25C shows a content of a 16-bit register in the CPU at every step of the program of Fig. 25A;

FIG. 26 is a multi-CPU system schematically shows according to an embodiment of this invention;

Fig. 27 shows the memory locations used in the multiple CPU system of Fig. 26;

Fig. 28 schematically shows another embodiment of this invention;

FIG. 29 is an additional embodiment schematically illustrates this invention;

FIG. 30 shows a flow chart for explaining the operation of the data processing system from FIG. 29.

An exemplary embodiment is described below with reference to the figures of this invention.

Fig. 12 shows a structure of a memory element according to an embodiment of this invention. According to FIG. 12, the memory element 100 is an 8-bit EPROM for storing data of the even-numbered address and an 8-bit EPROM 10 for storing data of the odd-numbered address, and includes an EPROM whose access with data lengths of both 16 bit and 8 bits is also possible.

The memory element 100 has a decoder circuit 150 which selectively connects the 8 bit data input / output terminal 63 of the even address EPROM 9 with the data input / output terminal 5 (lower data bus) of the lower 8 bits of the memory element in response to the least significant Address signal A 0 , which determines the even-numbered address / odd-numbered address and connects an output enable signal, and has a decoder circuit 200 which selectively connects the data input / output terminal 73 of the EPROM 10 for the odd-numbered address with the upper 8-bit data bus 6 (upper 8-bit data output connector of the memory element 100 ) or with the lower 8-bit data bus (lower 8-bit data output connector of the memory element) in response to the least significant address signal A 0 , upper data activation signal and the mode-selecting (bit-length-selecting) signal BYTE connects.

The decoder circuit 150 instructs a path for reading data of the EPROM 9 in response to the least significant address signal A 0 and the output enable signal OE, and a path for writing data applied to the lower 8-bit data bus 5 the data input terminal 63 of the EPROM 9 for the odd address in response to the least significant address signal A 0 and the output enable signal.

The read path has an inverter 21 for inverting and outputting the output enable signal, an inverter 22 for inverting and outputting the least significant address signal A 0 , a NAND gate 23 for outputting the negative logical product of the outputs of the inverters 21 and 22 and a read transfer gate 15 which turns on in response to the output of the NAND gate 23 for connecting the data input / output terminal 63 of the EPROM 9 to the lower 8-bit data bus 5 .

The write path has a NAND gate 27 for outputting the negative logic product of the output enable signal and the output of the inverter 21 , and a write transfer gate 16 which selectively connects the data input / output terminal 63 with the lower 8 bit data bus 5 in response connects to the output of the NAND gate 27 . Both transmission gates 15 and 16 become conductive when an "L" signal is applied to their control terminals.

The decoder circuit 200 has a path for connecting the data input / output connection 73 of the EPROM 10 to the lower 8-bit data bus 5 and a path for connecting the data input / output connection 73 to the upper 8-bit data bus 6 .

The path for connecting the lower 8-bit data bus 5 has a read path and a write path. The read path to the lower 8 bit data bus 5 has a NAND gate 24 which causes the negative logic product of the least significant address signal A 0 , the output of inverter 21 and the BYTE signal, and a read transfer gate 17 which in response becomes conductive to the output of NAND gate 24 . The write path includes a NAND gate 28 which provides the negative logic product of the least significant address signal A 0 , output enable signal and the BYTE signal, and a write transfer gate 18 which is responsive to the output of the NAND gate 28 switches on. The transfer gates 17 and 18 turn on when an "L" signal is applied to the respective control input terminals, and connect data output terminals 73 of the EPROM 10 to the lower 8-bit data bus 5 , respectively.

Similarly, the connection path to the upper 8-bit data bus 6 has a write path and a read path. The write path includes an inverter 29 for inverting and outputting the - signal, an inverter 30 for inverting and outputting the BYTE signal, a NAND gate 25 which causes the negative logic product of the outputs of the inverters 21, 29 and 30 , and one Read transfer gate 19 , which turns on in response to the output of NAND gate 25 . The write path includes a NAND gate 31 which provides the negative logic product of the output of inverter 29 , the output of inverter 30 and the output enable signal, and a write transfer gate 20 which is responsive to the output of NAND gate 31 switches on. The transmission gates 19 and 20 both turn on when an "L" signal is applied to the respective control input terminals and connect the data input / output terminal 73 of the EPROM 10 to the upper 8 bit data bus 6 . In the structure described above, the switching of the connection terminal of the data input / output terminal 73 of the EPROM 10 for the odd address is carried out by the BYTE signal.

The memory element 100 has an address input connection connected to the address bus 4 , lower 8 bit data input / output connections connected to the lower 8 bit data bus, a chip release input connection 11 for receiving the chip release signal, an output release Terminal 12 for receiving the output enable signal, a supply terminal 33 for receiving the supply voltage V _cc , a high voltage terminal 13 for receiving the high voltage V _pp for programming, a BYTE terminal 14 for receiving the BYTE signal, one with the upper one 8 bit data bus 6 connected upper 8 bit data input connection, and a connection for receiving the byte high enable signal. In the construction of FIG. 12, the data buses 5 and 6, the address bus 4 and the signal line 7 also show, respectively, the input / output terminals of the storage member 100. EPROMs 9 and 10 each have address input connections 61 and 71 , data input and output connections 63 and 73 , supply connections 60 a and 70 a , chip release connections 64 and 74 , output release connections 62 and 72 and high voltage connections 60 b and 70 b on.

Fig. 13 shows the relationship between the modes of the EPROM shown in Fig. 12 and the signals applied to each input terminal corresponding to each of the modes. As shown in Fig. 13, the EPROMs assign a read mode, an output blocking state (the state in which the data output terminal is in the flooded state), an idle state in which the EPROMs are not accessed, a program state to which the program is written, a program check state for checking the written program, and a program lock state. The program lock state indicates the state in which a program cannot be written from the outside, even if the high voltage Vpp is applied for programming. The operation of the memory element according to an embodiment of this invention is described below with reference to FIGS. 12 and 13.

First, the description follows of the case where a voltage having an "L" level is applied to the BYTE terminal 14 .

EPROMs 9 and 10 have the same construction as EPROMs 2 and 3 shown in FIG. 1. The following is a description of a case where the CPU (not shown in Fig. 12) accesses the EPROM, that is, the memory element 100 accesses in 16 bits. At this point, the address signals A 0 to A 14 , which appear on the address bus 4 as odd address signals, and the least significant signal A 0 have a "0"("L") level. 14 bit address signals A 1 to A 14 are applied to the respective address input terminals 61 and 71 of the respective EPROMs 9 and 10 . When the address of the address bus 4 is set up, the byte high enable signal BHE and the chip enable signal from the CPU go into the active state "L". In response to the signal and the signal, the address signals on the address data bus 4 are adopted in the EPROMs 9 and 10 of the memory element. When reading the data of the EPROM, the chip enable signal which is applied to the chip enable terminal 11 in synchronization with the signal and the output enable signal which is applied to the terminal 12 both go on the "L" level. At this point, the output enable signal is at the "L" level, so that the output of the inverter 21 becomes "H". Since the least significant address signal A 0 is also at "L", the output of the inverter 22 is now also "H". Therefore, the output of the NAND gate 23 which receives the outputs of the inverters 21 and 22 becomes "L" level and the transfer gate 15 is turned on. On the other hand, the output of the NAND gate 27 , which receives the output enable signal and the output of the inverter 22 , becomes "H" level and the transfer gate 16 is turned off. As a result, the 8 bit data input / output terminal 63 of the EPROM 9 is connected to the lower 8 bit data bus 5 . In the odd address EPROM 10 since the BYTE signal is at the "L" level, the outputs from both NAND gates 24 and 28 are at the "H" level and the transfer gates 17 and 18 are closed. This isolates the data input / output port 73 of the EPROM 10 from the lower 8 bit data bus 5 . Now that the signal is at the "L" level, the output of the inverter 29 is at the "H" level. Since the BYTE signal is at the "L" level, the output of the inverter 30 is also at the "H" level. Since the outputs of the inverters 21, 29 and 30 are at "H", the output of the NAND gate 25 becomes "L" so that the transfer gate 19 turns on. On the other hand, the output enable signal OE with "L" level is applied to the NAND gate 31 , so that its output becomes "H" level and the transmission gate 20 turns off. Therefore, for reading data, the data input / output terminal 73 of the EPROM 10 for the odd address is connected to the upper 8-bit data bus via the transfer gate 19 . As a result, 16 bit data is read.

If the CPU reads data in 8 bits in this 16-bit bus mode, there are 2 signal states on the condition that the BYTE signal is "L" level. Chip enable signal, output enable signal and byte high enable signal are at "L" level and the least significant address bit signal A 0 is at "1"("H") level (state, and Chip enable signal, output enable signal and the least significant address signal A 0 are at "L" level and the bit high enable signal is at "H" level (state. In the former signal state it is At this point, since the output of the inverter 22 becomes "L", the outputs of the NAND gates 23 and 27 both become "H" level and the transfer gates 15 and 16 both turn off / -Output connection 63 of the EPROM 9 for the even-numbered address and the lower 8-bit data bus isolated from one another On the other hand, since the byte high enable signal is at "L" level, the output of the inverter 29 is open "H", and since the BYTE signal is at "L", the output of inverter 30 is at "H". At this point, the output is g of the inverter 21 to "H". Therefore, the outputs of the NAND gates 24, 28 and 31 become "H" level, and only the output of the NAND gate 25 becomes "L" level. As a result, an "L" signal is applied only to the control input of the transmission gate 19 to turn it on. As a result, the data input / output terminal 73 of the odd address EPROM 10 is connected to the upper 8-bit data bus 6 . Therefore, the data in an odd address is read on the upper 8 bit data bus 6 .

In the state, since the byte high enable signal is "H" level, the output of the inverter 29 becomes "L" level and the outputs of the NAND gates 25 and 31 both become "H" level. As a result, both transmission gates 19 and 20 switch off. Therefore, the odd address data input / output port 73 of the EPROM is isolated from both the upper data bus 6 and the lower 8 bit data bus 5 . Since the address signal designates an even numbered address, the least significant address signal A 0 is now at the "L" level and the output of the inverter 22 is at the "H" level. On the other hand, since the output enable signal is at the "L" level, the output of the inverter 21 becomes "H" level. Thereby, the output of the NAND gate 23 is set to "L" level, the output of the NAND gate 27 is set to "H" level, only the transfer gate 25 is turned on and the data input / output terminal 63 of the EPROM 9 for the odd number Address is connected to the lower 8 bit data bus 5 . As a result, the data of the even-numbered address is read onto the lower 8-bit data bus 5 .

Next is a description of a case where the BYTE signal is "H" level. Access to memory element 100 is blocked in 16 bits and the CPU can only access the 8 bit data. There are two cases for the signal state, namely access to the EPROM 9 for the even-numbered address (state) and access to the EPROM 10 for the odd-numbered address (state. In the first-mentioned state, the output enable signal and the am least significant address signal A 0 is both at the "L" level and the byte high enable signal is at the "H" level In the latter condition, the output enable signal and the byte high enable are Signal both at "L" level and the least significant address signal A 0 is at "H" level. In this state, the output of NAND gate 23 becomes "L" level, the output of NAND gate 27 "H" level, and only the transfer gate 15 is turned on, thereby connecting the data input / output terminal 63 of the EPROM 9 to the lower 8 bit data bus 5 as described above. On the other hand, since the byte High enable signal is at the "H" level, the Au output of the inverter 29 "L" - level. As a result, the outputs of NAND gates 25 and 31 both become "H" level and transmission gates 19 and 20 both turn off. Even if the BYTE signal is "H" level, both NAND gates 24 and 28 output "H" level signals because the least significant address signal A 0 is at the "L" level and the even number and the output enable signal is at the "L" level. As a result, both transmission gates 17 and 18 turn off and EPROM 10 is disconnected from data input / output buses 5 and 6 . Therefore, the data of the even-numbered address is only read in from the lower data bus 5 .

In the state, since the least significant address signal A 0 is at "H" level, the output of inverter 22 becomes "L" level and NAND gates 23 and 27 both output signals at "H" level . As a result, both transmission gates 15 and 16 switch off. As a result, the data input / output terminal 63 of the EPROM 9 for the odd address is isolated from the lower data bus 5 . In this state, the high byte enable signal is now at the "L" level and the BYTE signal is at the "H" level. As a result, the output of the inverter 30 which receives the BYTE signal becomes "L" level. As a result, the outputs of NAND gates 25 and 31 both become "H" and transfer gates 19 and 20 both turn off and are isolated from upper data bus 6 . In this state, the output of inverter 21 , the BYTE signal, and the least significant address signal A 0 are all at "H" level, so that all inputs of NAND gate 24 are "H" level signals. Therefore, the output of the NAND gate 24 becomes "L" level and the transfer gate 17 turns on. On the other hand, since the NAND gate 28 receives the output enable signal at the "L" level, the output thereof becomes "H" level and the transmission gate 18 turns off. As a result, the 8 bit data input / output port 73 of the odd address EPROM 10 is connected to the lower 8 bit data bus and the 8 bit data of the odd address appear on the lower data bus 5 .

Next, a description will be given of a case in which data is written into the EPROMs 9 and 10 with an 8-bit PROM writer. In this case, the BYTE signal is first set to the "H" level. In this state, the output of the inverter 30 receiving the BYTE signal becomes "L" level, so that the outputs of the NAND gates 25 and 31 both become "H" level and the transmission gates 19 and 20 both turn off. To write data in this state, the chip enable signal becomes "L" level and the output enable signal becomes "H" level. To program the data, the high voltage Vpp is raised to 12.5 V for programming and the supply voltage Vcc is also raised to 6 V. The following is a description of a case in which the 8-bit data to be written has the even-numbered address, with the least significant address signal A 0 being at the "L" level. The output of the inverter 22 becomes "H" level and the output of the inverter 21 becomes "L" level. As a result, the output of the NAND gate 27 becomes "L" level and the transfer gate 16 is turned on. Since the output of the inverter 21 is at "L" level, the output of the NAND gate 23 becomes "H" level and the transfer gate 15 is turned off. As a result, the data appearing on the lower 8 bit data bus 5 is written into the data input terminal 63 of the EPROM 9 via the transfer gate 16 . On the other hand, when the address for data to be written is even, that is, when the least significant address signal A 0 is at "H" level, the byte high enable signal becomes "L" level. Since the BYTE signal BYTE is at the "H" level, the outputs of the NAND gates 25 and 31 are both brought to the "H" level by the inverter 30 and the transmission gates 19 and 20 are turned off. Meanwhile, the address signal A 0 is at the "L" level and the output of the inverter 21 is at "L", so that the output of the NAND gate 24 becomes "H" - and the output of the NAND gate 28 reaches the " L "level is maintained. As a result, the transmission gate 17 turns off and the transmission gate 19 turns on. As a result, in this state, the 8-bit data having an odd address is written over the lower data bus 5 and the transfer gate 18 .

The program lock state is the same as the data write state (program state), however, since the chip enable signal is at the "H" level, neither the EPROM 9 and 10 and 10 and because the output enable signal is at the "H" level "Level, data input / output is not performed. In the program check state, the output enable signal is at "L" level, and the reading in of the written data is carried out in the same manner as in reading the data, and the check of the program data is performed. As a result, by selecting the BYTE signal level as a function of the even-numbered address and the odd-numbered address, data can be written using an 8-bit PROM recorder.

In the meantime, by determining the 8-bit access with the BYTE signal, the data only appear on the lower 8-bit data bus 5 .

Although the BYTE signal is externally applied by the CPU in the above-described form, data writing can be carried out automatically by using only the lower 8-bit data bus 5 in programming, including a comparator 91 which uses the high voltage Vpp for programming with the reference voltage Vref 1 , a comparator 92 which compares the supply voltage Vcc with the reference voltage Vref 2 , and an AND gate 93 which receives the outputs of the comparators 91 and 92 for generating the BYTE signal, as in FIG. 14 shown are provided.

Although the memory element described above has two 8-bit EPROMs, a 16-bit EPROM can be used instead of the structure described above to carry out the same operation. In particular, in the structure shown in Fig. 12, by replacing the data input / output port 73 of the EPROM 10 for the odd address with an upper 8 bit data input / output port and using the same decoder circuits 150 and 200, a 16 bit EPROM can be used Storage element can be set up.

Fig. 15 shows the connection in the system in which one Memory device which has, for example, a 16-bit EPROM, is connected to a 16 bit CPU. In the construction after Fig. 15 has the 16 bit CPU1 an address output port101  for the output of 15 bit addresses, a lower data input / - output connection102 for input and output of lower 8 bit Data, an upper 8 bit data input / output connector103 to Input and output of the upper 8 bit data, one byte high Release connection104 to output the byte high enable signal , a release port105 to output the release signal    to activate the memory and oneR/ -Signal output connector 106 to determine the memory read / write cycle on.

Meanwhile, the storage element100 athat in this Example implemented by the 16 bit EPROM and as a 16 Bit storage element alternatively also other 16 bit RAM or the like has an address input port201 to receive of 14 bit address signalsA 1 toA 14 via an address bus303, a lower data input / output connector202 for input and output of lower 8 bit data via a lower data bus301, a Connection203 for receiving the least significant address signal A 0 to select the even numbered address and the odd-numbered address, a data input / output connection204 to Input and output of the upper 8 bit data via an upper data bus 302, a byte high enable input port205 to receive of the byte high enable signal, a chip enable connector 206 to receive the release signal  from the CPU and one Exit enable connector207 for inverting and receiving the R /Signals from the CPU1 on. With this structure, the BYTE Input connector grounded. Therefore, the storage element100 a in Both 16 bit and 8 bit modes are described. If that Storage element100 a is implemented by a RAM the program mode in the EPROM the write mode. However, the High voltageVpp not generated for programming. The storage element contains the decoder circuits150 and200 outFig. 12.

Fig. 16 shows the timing of the operation of the memory element toFig. 15 in 16 bit bus mode. In the following the Operation of the 16 bit memory element according to another Embodiment of this invention with reference to the Fig. 15 and 16. With this structure, the BYTE Signal grounded and at "L". As with reference toFig. 12 In this case, the lower 8 bit data appear always on the lower 8 bit data bus301while the top 8  Bit data on the upper 8 bit data bus302 appear. In which namely, the structure described above is, if the byte high Enable signal determines the access in 16 bits by "L" even address signal on the address bus303 appear and the least significant address signalA 0 becomes "L" level. If the release signal  drops and the chip release connector 206 of the storage element100 a is activated, the appear Data for the even-numbered address on the lower 8-bit data bus 301 and the 8 bit data for the odd address appear on the upper 8 bit data bus302. At this point, through the read / write signalR / selected whether the data in that Storage element100 a to be written or not. If the output enable port207 is at the "L" level, he goes in reading mode and when it is at the "H" level, it goes into the write mode. In this state when the byte high enable Signal is at "H" and the address signalA 0 the even number Address, the 8-bit data is determined via the lower 8-bit Data bus301 read or written and, conversely, the 8-bit data of the odd-numbered address appear on the upper 8 bit data bus302.

Fig. 17 shows the connections at the 8 bits bus mode, in which only the lower 8-bit bus is used as a data bus of the CPU 1. According to FIG. 17, the BYTE-terminal of the memory element 100 is connected to a supply voltage Vcc and the BYTE signal is set at "H" level. In this case, either the even address information or the odd address information appears on the lower 8-bit data bus 301 in response to the "H" level or the "L" level of the least significant address signal A 0 , such as described above with reference to FIG. 12.

Fig. 18 shows the operation in FIG. 8 in a time chart Bit bus mode of the inFig. 17 shown system. ToFig. 18th the data of the even numbered address or odd numbered appear  Address on the lower 8 bit data bus301 in response to that Release signal  and according to the address signalsA 0 to A 14. With this structure, either the data of the odd number appears Address or the data of the even-numbered address on the Data bus301 in response to the address signalA 0.

The structure described above can be replaced by replacing the program Mode operation of the EPROM by the data write operation on the RAM can be applied. Therefore, with reference to the Figures the relationship between the register of the CPU and the 16th Bit data is described in a general 16 bit memory element.

Fig. 19 shows the relationship of the data appearing in the memory element in the 16-bit bus mode and the data bus. As shown in Fig. 19, when the BYTE signal is "L" level, the memory element is in 16-bit bus mode and can generate data of either 16-bit or 8-bit. However, in this case, the data D 0 to D 7 with an even-numbered address are output on the lower data bus and the data D 8 to D 15 with odd-numbered addresses appear on the upper 8-bit data bus, as is apparent from the above description. When 8-bit data is selected, for example, only the data with an even address on the lower data bus and if the byte- and the byte- are displayed in this state if the - signal = "H" and the least significant address signal = "L". High enable signal is set to "L" and the least significant address signal A 0 = "H" is set, only the data with an odd address appears on the upper data bus. In this case, read / write operations between the registers of the CPU and the memory element are performed in a one-to-one relationship in the same manner as in the conventional structure. This is because the upper data bus is connected to the upper register and the lower data bus to the lower register.

Fig. 20 shows the relationship between the address and data buses on which the information appears when the memory IC is used in the 8-bit bus mode. In this case the BYTE signal = "H" is set to set the 8 bit mode and only the lower 8 bit data bus is used. As a result, when the least significant address signal A 0 selects the even address by "L", the even address data appears on the lower data bus, and when the least significant address signal A 0 is at "H" level and the odd number If the address is selected, the odd-numbered address data input / output connection is connected to the lower data bus, regardless of the byte high enable signal. As a result, access to both the even-numbered address and the odd-numbered address is possible by using only the lower data bus.

Figs. 21 and 22 show the relationship between the registers of the CPU and the odd / even address of the memory element in the 8-bit bus mode. As shown in Fig. 17, when the BYTE signal is "H" and the mode is the 8-bit bus mode, if the address signal A 0 for odd selection is "1"("H"), the information becomes the odd number Transfer address to the lower register. This is possible, and reverse operation is also possible. The lower register of the CPU register is connected to the odd-numbered addresses of the memory element.

Next, as shown in FIG. 22, when the BYTE signal = "H" and the even address is determined, that is, the least significant address signal A 0 is at the "0"("L") level, Memory locations of the odd-numbered addresses are connected to the lower register of the CPU via the lower data path. If only the 8-bit data is required, the lower 8-bit register is therefore accessed directly for performing read / write operations without an exchange command. Since the contents of the lower register do not have to be transferred to the upper register via exchange commands or the like, the data processing speed can be increased significantly in comparison with the conventional device.

The improvement of the data processing according to this invention is described in detail using a specific program. Consider the case of the memory system of FIG. 23 in which the 16-bit CPU 500 executes data processing in accordance with the program shown in FIG. 25A.

According to Fig. 23, the 16 bit CPU 500, connected to an upper byte data bus DBH upper byte data line 513 and connected to a lower byte data bus DBL lower byte data line 514. A memory 510 for storing data with an odd address is selectively coupled to either the data bus DBH or the data bus DBL via a selector 700 . A memory 520 for storing data with an even address is selectively coupled to the data bus DBL via the selector 700 . The memory system of FIG. 23 has a memory map or memory locations as shown in FIG. 24.

As shown in FIGS. 25A to 25C, in the system according to the invention, the memories 510 and 520 are carried out independently of one another in the different program steps, a byte exchange command not being required, which simplifies the program and reduces the number of program steps becomes. Even if the program forms a loop, no time loss due to the byte exchange is added up, which provides for fast processing of 8-bit data.

In addition, if another 8-bit CPU 600 is provided to form a multiple CPU system as shown in Fig. 26, the 8-bit CPU 600 can be assigned to any memory location of Fig. 27 regardless of an even-numbered address or an odd-numbered address due to the selector 700 access.

Although the CPU in the above-described embodiment has a 16-bit structure and accesses in 8-bit and 16-bit, the CPU is not limited to this and may have a 32-bit structure, a 64-bit structure or larger bit structure, and the same effect as in the above-described embodiment can be obtained if the memory element is accessed with the number of bits representing the minimum access number of the CPU, as shown in FIG. 28. With respect to the memory device used, other than EPROM or RAM memory devices can be used, whereby the same effect as in the above-described embodiment is obtained.

Although in the above described embodiment the BYTE Signal is set to "H" or "L", it can be from the CPU in Depending on the work content.

Although in the embodiment described above, the selector for selectively coupling the lower data bus to either a lower byte memory or upper byte memory made of hardware Components is formed, can alternatively be a user-specific Configuration used to be a data processing system to provide with fast data processing.

According to Fig. 29, the data processing system, a data processing unit 800, the data into 2 ⁿ bits and 2 ^m bits (m ≦ λτ s) can handle, a flow control 850 with user specific structure for controlling the flow of data between the processing unit 800 and the memories 860, 870 , and first and second memories 860, 870 , each storing 2 ^n- bit data. The data bus 863 between the data processing unit 800 and the data flow controller 850 has upper data lines with 2 ⁿ bits and lower data lines with 2 ⁿ bits.

Fig. 30 is a flowchart for explaining the operation shown by the flow control 850th The operation of the data flow controller will be briefly described with reference to Figs. 29 and 30.

If the controller decides that the transfer of complete 2 ^m bit data by processing unit 800 (step 10) is required, controller 850 connects 2 ⁿ bit data buses 861, 862 to 2 ^m bit data bus 863 in parallel (step 12 ).

If controller 850 decides that only lower data is to be transferred (step 14), controller 850 connects the 2 ⁿ bit data bus 861 for first memory 860 to the lower data lines that are in 2 ^m bit data bus 863 are included (step 16). If the lower data is not requested, the program continues to decision block ( S 18 ) to decide whether access to the second memory 870 is required via the upper data lines contained in the 2 ^m bit data bus 863 . If the decision is affirmative, the data bus 862 is connected to the upper data lines contained in the data bus 863 (step 20). If the decision is negative, the data bus 862 is coupled to the lower data lines contained in the data bus 863 (step 22).

As described above, in a system according to this invention with a CPU with 2 ^m bit structure, which can be accessed in at least 2 ⁿ bits ( m ≦ λτ n ), and with a memory element, which is both in 2 ⁿ bits can also be accessed in 2 ^m bits, only the lower 2 ⁿ bit data bus is selectively used to connect the CPU and the memory element in response to the upper address activation signal and a bus selection signal (bit length selection signal) for access in 2 ⁿ bits. This allows the desired address of the memory IC to be connected to the lower register of the CPU if the need arises. Furthermore, since an exchange command or the like is not required during data processing, the data can be processed at high speed. In addition, the upper 2 ⁿ bit data can selectively appear on either the corresponding upper data bus or the lower data bus, whereby memories with 2 ⁿ bit structure in the CPU with 2 ^m bit structure such as 16 bit or 32 bit are used and without problems operate.

If the memory element contains a multiplicity of EPROMs with 8 bit Furthermore, programming can always have structure by using only the lower 8 bit data bus so that the data can be transmitted through a conventional 8 bit PROM Writers can be enrolled. This allows EPROMs always get the right pair of information save because the corresponding relationship between the even number Address and the odd-numbered address of the data during of the writing process is accepted without errors. Because of this In addition, data stored in a conventional 8 Bit CPU represent the basic data, in the upper 16 bits, etc., CPU can be used, making a powerful microcomputer can be used while maintaining the stand's processes the technology, which increases the performance of existing computer systems can be easily increased.

Claims (6)

1. memory element which can be accessed at least in 2 ⁿ bits (n is an integer) and 2 ^m ( m ≦ λτ n ) has first data input / output connections ( 5, 6 ), and furthermore a memory device ( 9 , 10 ) with 2 ^m second data input / output connections ( 63, 73 ), characterized by :
a connection ( 14 ) for receiving a signal (BYTE) which determines the bit length of the data which access the memory device ( 9, 10 ),
a terminal ( 4, 7 ) for receiving an address selection signal for determining the address which is accessed in the memory device ( 9, 10 ) and
a connecting device ( 150, 200 ) for connecting data input / output connections, the number of which is determined by the bit length signal from the 2 ^m second data input / output connections ( 63, 73 ), to a lower data input / output connection ( 5 ) from the first input / output terminals ( 5, 6 ) in response to the bit length signal and the address selection signal. 2. Memory element according to claim 1, characterized in that the memory device ( 9, 10 ) has even-numbered addresses and odd-numbered addresses, each of which selects a memory location for 2 ⁿ bit data, and, if the bit length signal determines 2 ^m bit, on subsequent ones Addresses from an odd-numbered address and an even-numbered address are formed simultaneously to form 2 ^m bit data, the odd-numbered address determining upper data and the even-numbered address determining lower data, and, if the address selection signal is upper data, resulting in an odd-numbered Address is determined and the bit length signal determines 2 ⁿ bits, the selective connection device ( 150, 200 ) the 2 ⁿ data input / output connections, the address, which from the second data input / output connections ( 63, 73 ) through the address selection signal is selected corresponds, with the lower 2 ⁿ data input / output connections of the first input / output connections ( 5, 6 ) ve binds. 3. Storage element according to claim 1, characterized in that the address select signal is an upper data enable signal and an Signal that indicates whether the memory address to be accessed is an upper address or a lower address, having. 4. Memory element according to one of claims 1 to 3, characterized in that the selective connection device ( 150, 200 ) has a first decoder device ( 150 ) for the lower address data input / output connection of the first and second data input / output connections ( 5, 6, 63, 73 ) and an output enable signal and a signal indicating whether the lower / upper memory address for determining whether a lower address is being accessed, and a second decoder device ( 200 ) which is provided for the upper address data input / output connections of the first and second data input / output connections ( 5, 6, 63, 73 ) and which receives the bit length signal, the upper / lower selection signal and the upper address data activation signal for determining that a upper address is accessed and that the accessed upper second data input / output ports are required for connection to lower first data input / output ports. 5. Data processing system for the selective processing of data in 2 ⁿ and 2 ^m bits with a memory element which can be accessed at least in 2 ⁿ bits ( n is an integer) and which 2 ^m ( m ≦ λτ n ) first data Has input / output connections ( 5, 6 ), and furthermore has a memory device ( 9, 10 ) with 2 ^m second data input / output connections ( 63, 73 ), characterized in that the memory element has:
a connection ( 14 ) for receiving a signal (BYTE) which determines the bit length of the data which access the memory device ( 9, 10 ),
a terminal ( 4, 7 ) for receiving an address selection signal for determining the address which is accessed in the memory device ( 9, 10 ) and
a connecting device ( 150, 200 ) for connecting data input / output connections, the number of which is determined by the bit length signal from the 2 ^m second data input / output connections ( 63, 73 ), to a lower data input / output connection ( 5 ) from the first data input / output terminals ( 5, 6 ) in response to the bit length signal and the address selection signal. 6. Access method for a memory which can be accessed at least in 2 ⁿ bits ( n is an integer) and which has 2 ^m ( m ≦ λτ n ) first data input / output connections ( 5, 6 ), and furthermore has a memory device ( 9, 10 ) with 2 ^m second data input / output connections ( 63, 73 ), characterized in that the method comprises the steps:
Receiving a signal (BYTE) for determining a bit length of the data which access the memory device ( 9, 10 ),
Receiving an address selection signal to determine the address accessed in the memory device ( 9, 10 ) and
Connect data input / output connections, the number of which is determined by the bit length signal from the 2 ^m second data input / output connections ( 63, 73 ), to a lower data input / output connection ( 5 ) from the first data inputs - / Output terminals ( 5, 6 ) in response to the data bit length signal and the address selection signal.