JPH01201890A - Read only memory control circuit - Google Patents

Abstract

PURPOSE:To reduce energy consumption in a command decoder circuit, a clock generating circuit, etc., by providing a chip selecting terminal at an ROM, selectively impressing a selecting signal, and operating the ROM only at the time of an impression. CONSTITUTION:The command decoder circuit consists of an ROM 1, a chip selecting terminal 2 to be a chip enable terminal, an input terminal line 3, an inverter 4 provided between the terminal 2 and the terminal line 3, and a latch circuit 5 provided between the terminal 2 and the ROM 1 and composed of FFs. In such a constitution, a command instructing signal from a processor and a circumferential circuit, which are not shown in a figure, is impressed to the input terminal line 3, made into the input signal of the inverter 4, and an interted signal from here is applied to the selecting terminal 2 and the latch circuit 5. Thus, the chip of the ROM 1 is selected, the address signal at 8 bits to be a command input is inserted into the ROM 1, and data corresponding to it are latched by a reading circuit 5, and a control signal is outputted from here.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 5 and 6) Problems to be solved by the invention Means for solving the problems (Figure 1) Working examples (Fig. 2, Fig. 3, Fig. 4) Effects of the invention [Summary] Regarding a read-only memory control circuit, for the purpose of reducing average power consumption, a chip selection terminal is provided in a read-only memory. A chip selection signal is selectively applied to the chip selection terminal, and the read-only memory is brought into operation only when the chip selection signal is applied.

[Industrial application field]

The present invention is applicable to read-only memory (ROM) used in command decoding circuits, clock generation circuits, etc.
Regarding the control circuit of 1. In particular, the present invention relates to a read-only memory control circuit that can reduce average power consumption.

[Conventional technology]

Conventionally, command decoding circuits and clock generation circuits using read-only memory (ROM), such as those shown in FIGS. 5 and 6, have been known.

FIG. 5 is a schematic diagram of the command decoding circuit, l
O is read-only memory (ROM), 1) is ROM
l0 chip selection terminal (chip enable terminal: CE)
, 12 is a flip-flop circuit as a latch circuit,
13 is an inverter.

The above-mentioned chip selection terminal 1) is a terminal to which a chip enable signal is applied in order to select the chip of ROM10, but in this example, since chip selection terminal 1) is grounded, this chip is always selected. It is designed to be used in the same condition.

This command decoding circuit decodes, for example, an 8-bit command input signal, which is an input signal to the flip-flop circuit 12, into a 4-bit control signal, which is an output signal of the ROM10, and outputs the decoded signal.

In this case, by inputting a command instruction signal from a processor or a peripheral circuit (not shown), etc. to the inverter 13, and applying an output signal (inverted signal) of the inverter 13 to the flip-flop circuit 12, the command input signal is After latching, a signal is always output as an address input signal for the selected ROM.

When this 8-bit address signal is input to ROM10, the corresponding data is read out of the stored data in ROM10, and a 4-bit control signal, that is, a decoded output signal is output.

FIG. 6 is a schematic diagram of the clock generation circuit, and 10 is R
OM, 1) is the chip selection terminal (chip enable terminal:
CE), 14 is an address counter, and 15 is an input terminal.

In this example as well, chip selection terminal 1 provided in ROMl0
) is grounded, and like the one in Figure 5, the ROM1
0 is always selected.

This clock generation circuit reads data in the ROM10 and outputs a clock output based on a specific level signal of the master clock applied to the input terminal 15.

That is, the master clock applied to the input terminal 15 is counted by, for example, a 4-bit output address counter 14, and
The 4-bit output of this address counter is used as an address signal to read out the clock pattern stored in ROM10, and the output of ROM10 is input to flip-flop 12 as a latch circuit for shaping and outputting a clock. It is.

In this case, since the chip selection terminal 1) of ROM10 is always grounded, ROM10 is always selected.

[Problem to be solved by the invention]

In this way, in ROMs used in conventional command decode circuits, clock generation circuits, etc., the chip selection terminal (chip enable terminal) is always grounded.
The disadvantage was that the average power consumption of the ROM was large.

That is, ROMs generally have the property of consuming less power when no chip is selected.

In particular, in a 0MO3 EFROM, the power consumption in the standby state is extremely low, theoretically 0 (actually, the leakage current is extremely small on the order of μA).

However, when the chip selection terminal is always grounded, the leakage current is large, and the average power consumption of ROM0 becomes large as a whole.

The present invention has been made to solve these conventional drawbacks, and aims to reduce average power consumption while retaining the conventional functions.

[Means to solve the problem]

In order to achieve the above object, the present invention is as follows. That is, FIG. 1 shows a diagram for explaining the principle of a ROM control circuit according to the present invention, and the present invention will be described in detail below based on this diagram.

As shown in FIG. 1, the ROM 1 is provided with a chip selection terminal (chimbu enable terminal 2σT-) 2 for chip selection, and an input terminal line 3 is connected to this chip selection terminal 2. There is.

[Effect]

When a chip selection signal is applied to input terminal line 3, ROMI
is in the operating state and, for example, when an 8-bit address signal is input, the data corresponding to this address is read out,
For example, it produces a 4-bit ROM output.

Further, when no chip selection signal is applied to the input terminal line 3, the ROMI is in a non-selected state, and the chip selection terminal 2 is in an open state.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. Second
The figure shows the configuration of an embodiment of the present invention, and shows an example implemented in a command decoding circuit (corresponding to the conventional example shown in FIG. 5).

In Figure 2, 1 is a ROM, 2 is a chip selection terminal (chip enable terminal), 3 is an input terminal line with an input terminal formed at its tip, 4 is an inverter, and 5 is a flip-flop as a latch circuit. It is a circuit.

This command decoding circuit applies a command instruction signal from a processor or a peripheral circuit (not shown) to an input terminal line 3 as a human input signal to an inverter 4, and outputs the output (inverted output) of the inverter 4 to a chip selection terminal 2 of a ROMI.
(CB) and applied to flip-flop 5. This command instruction signal selects the ROMI chip, and an 8-bit address signal, which is a command input, is taken into the ROM1.

Thereafter, data corresponding to the address signal is read out and latched by the flip-flop circuit 5, and a control signal is issued.

When the command instruction signal to the input terminal line 3 disappears, the chip enters a non-selected state and stops.

FIG. 3 shows a second embodiment of the present invention, which shows an example of use in a clock generation circuit (corresponding to the conventional example shown in FIG. 6).
It is.

In FIG. 3, the same reference numerals as in FIG. 2 indicate the same parts. Note that 6 is an address counter.

This clock generation circuit counts the master clock signal applied to the input terminal line 3 with an address counter 6, reads out data using the output signal of the address counter 6 as a ROMI address signal, and uses it as a clock output signal. It is.

That is, by using the L level (low level) and H level (high level) of the mask clock signal applied to the input terminal line 3, when the master clock signal is at the L level, the RO
Set MI to the selected state, and change from L level to H level to R.
Set OMI to selected state.

In this ROMI selection state, the ROMI output signal is output, so after this output signal is latched by the free knob flop circuit 5, a clock output signal is output and the address counter 6 is counted up by +1. do.

Also, at this time, since the mask clock signal is at H level at the same time, ROMI is in a non-selected state.

Thereafter, similar operations are repeated to sequentially output clocks.

FIG. 4 is a waveform diagram of each part in the embodiment shown in FIG. 2.

(A) is a command input signal, that is, a part of the ROMI address input signal, (B) is a command instruction signal, (C) is a chip enable signal, and the command instruction signal shown in (B) is a diagram showing a part of the address input signal of ROMI. This is the signal that is inverted by an inverter.

(D) is an output signal of ROMI, which is a signal delayed from the command instruction signal. (E) is an output signal of the flip-flop circuit 5, and (F) is a command output signal, that is, a control signal output as an output signal of the flip-flop circuit 5.

〔Effect of the invention〕

As explained above, the present invention has the following effects.

(1) In the command decoding circuit shown in Fig. 2, the ROM is conventionally selected only at the timing when it was latched at the stage before the ROM, the latching at the stage before the ROM is omitted, and the latching at the stage before the ROM is omitted, and instead it is latched at the stage before the ROM. By adding a latch to the device, it is possible to reduce average power consumption while still providing conventional functionality.

+2) Compared to the conventional one where ROM is always selected (compared to
The command decode circuit of the present invention, which selects the ROM only when the state changes, has lower average power consumption.

(3) In the clock generation circuit shown in Fig. 3,
As in the case of the command decoding circuit described above, since the ROM is selected only when necessary, the average power consumption is reduced.

(4) Furthermore, in the above clock generation circuit, the average power consumption can be reduced as the L level (low level) time of the master clock is shorter with respect to the period of the master clock.

Therefore, it is advantageous in the thermal design of a package implementing this circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a configuration diagram of a first embodiment in which the present invention is implemented in a command decoding circuit. FIG. 3 is a configuration diagram of a second embodiment in which the present invention is implemented in a clock generation circuit. 4 is an explanatory diagram of the operation of FIG. 2, FIG. 5 is a conventional command decoding circuit, and FIG. 6 is a conventional clock generation circuit. 1-1-Read-only memory 2--chip selection terminal 3--input terminal line 4--inverter 5-flip-flop circuit 6--address counter

Claims (3)

[Claims] (1) A chip selection terminal (2) is provided in the read-only memory (1), and a chip selection signal is selectively applied to this chip selection terminal (2), and only when the chip selection signal is applied. , this lead
A read-only memory control circuit characterized by putting a only memory into an operating state. (2) In the read-only memory control circuit according to claim (1), a latch circuit (5) which is latched by a command instruction signal functioning as a chip selection signal is provided on the output side of the read-only memory. The read-only memory is brought into an operating state only when a command instruction signal is applied, and at the same time, the latch circuit (5) is brought into a latched state, and the command input signal of the read-only memory is stored as an address signal. A read-only memory control circuit characterized in that it reads data and produces a decoded output on the output side of the latch circuit (5). (3) In the read-only memory control circuit according to claim (1), a master clock signal functioning as a chip selection signal is counted and the output thereof is input to the input side of the read-only memory as a read-only memory control circuit. In addition to providing an address counter (6) that outputs an address signal for the memory, a latch circuit (5) that is latched by the master clock signal is provided on the output side of the read-only memory, so that the master clock signal is The latch circuit (5) puts the read-only memory into operation only when the latch circuit (5)
A read-only memory control circuit characterized in that it outputs a clock signal from.