JPS6488655A - Memory circuit for picture processing - Google Patents

Memory circuit for picture processing

Info

Publication number
JPS6488655A
JPS6488655A JP24547087A JP24547087A JPS6488655A JP S6488655 A JPS6488655 A JP S6488655A JP 24547087 A JP24547087 A JP 24547087A JP 24547087 A JP24547087 A JP 24547087A JP S6488655 A JPS6488655 A JP S6488655A
Authority
JP
Japan
Prior art keywords
address
data
picture
picture processing
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24547087A
Other languages
Japanese (ja)
Inventor
Hiromi Kiyomiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24547087A priority Critical patent/JPS6488655A/en
Publication of JPS6488655A publication Critical patent/JPS6488655A/en
Pending legal-status Critical Current

Links

Landscapes

  • Image Input (AREA)

Abstract

PURPOSE:To execute a picture processing at a high speed by reading simultaneously even picture data near a circumference together with the picture data when the picture element is designated by an address. CONSTITUTION:At the time of READ, address data are outputted to an X decoder 9 and a Y decoder 10 and by the READ signal from an R/W control circuit 12, respective decoders 9 and 10 generate a different address. The data near 8 with an X address and a Y address as a center are outputted for respective pages. A data control circuit 11 receives the output of respective pages by a READ signal and outputs it to an external part. Thus, at the time of READ, the bit data of the designated address and the bit data near 8 are outputted and the high speed of a picture processing system can be executed.
JP24547087A 1987-09-29 1987-09-29 Memory circuit for picture processing Pending JPS6488655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24547087A JPS6488655A (en) 1987-09-29 1987-09-29 Memory circuit for picture processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24547087A JPS6488655A (en) 1987-09-29 1987-09-29 Memory circuit for picture processing

Publications (1)

Publication Number Publication Date
JPS6488655A true JPS6488655A (en) 1989-04-03

Family

ID=17134138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24547087A Pending JPS6488655A (en) 1987-09-29 1987-09-29 Memory circuit for picture processing

Country Status (1)

Country Link
JP (1) JPS6488655A (en)

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