JPS55138132A - Signal processor - Google Patents

Signal processor

Info

Publication number
JPS55138132A
JPS55138132A JP4574779A JP4574779A JPS55138132A JP S55138132 A JPS55138132 A JP S55138132A JP 4574779 A JP4574779 A JP 4574779A JP 4574779 A JP4574779 A JP 4574779A JP S55138132 A JPS55138132 A JP S55138132A
Authority
JP
Japan
Prior art keywords
terminal
control data
processing
signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4574779A
Other languages
Japanese (ja)
Other versions
JPS6155135B2 (en
Inventor
Seiichiro Shigaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4574779A priority Critical patent/JPS55138132A/en
Publication of JPS55138132A publication Critical patent/JPS55138132A/en
Publication of JPS6155135B2 publication Critical patent/JPS6155135B2/ja
Granted legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To bring excellent signal processing to effect by letting a digital signal processor, using a stored program, operate at its original processing speed without reference to whether a control data write instruction exists to send control data to a processing circuit according to the existence of the write instruction.
CONSTITUTION: Memory 8, when write command signal wp is not supplied to terminal W/R, outputs control data stored at read address (ar) from address output terminal AO of processing circuit 9 to terminal CI of circuit 9. On the other hand, when signal wp is supplied to terminal W/R, control data (dw) from terminal 2 is written at an address assigned by address (ar) while data (dw) are output, and circuit 9 processes input signal Si from terminal SIP on the basis of data (dw) and outputs the processing result data to terminal 5. Consequently, circuit 9 operates at its original processing speed without reference to whether signal wp control data write instruction (w) exists and also inputs control data (dw) to the processing circuit according to the existence of write insturction (w), performing excellent signal processing.
COPYRIGHT: (C)1980,JPO&Japio
JP4574779A 1979-04-13 1979-04-13 Signal processor Granted JPS55138132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4574779A JPS55138132A (en) 1979-04-13 1979-04-13 Signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4574779A JPS55138132A (en) 1979-04-13 1979-04-13 Signal processor

Publications (2)

Publication Number Publication Date
JPS55138132A true JPS55138132A (en) 1980-10-28
JPS6155135B2 JPS6155135B2 (en) 1986-11-26

Family

ID=12727898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4574779A Granted JPS55138132A (en) 1979-04-13 1979-04-13 Signal processor

Country Status (1)

Country Link
JP (1) JPS55138132A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61183727U (en) * 1985-05-09 1986-11-15

Also Published As

Publication number Publication date
JPS6155135B2 (en) 1986-11-26

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