JPS5566021A - Communication control unit - Google Patents

Communication control unit

Info

Publication number
JPS5566021A
JPS5566021A JP13788278A JP13788278A JPS5566021A JP S5566021 A JPS5566021 A JP S5566021A JP 13788278 A JP13788278 A JP 13788278A JP 13788278 A JP13788278 A JP 13788278A JP S5566021 A JPS5566021 A JP S5566021A
Authority
JP
Japan
Prior art keywords
bit
circuit
transferred
receiving
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13788278A
Other languages
Japanese (ja)
Inventor
Toshiharu Ogasawara
Shigetoshi Suwa
Shigeru Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13788278A priority Critical patent/JPS5566021A/en
Publication of JPS5566021A publication Critical patent/JPS5566021A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make a program processing rapid and make it possible to cope with the receiving processing of a high-speed circuit and many circuits sufficiently by discriminating receiving data and the state of a communication control unit by hardware.
CONSTITUTION: Receiving data from a communication circuit is stored temporarily in receiving buffer 2, and is transferred to main storage device 10 after code discrimination in 3 [the discrimination result is stored in state hold circuit 4 (bit 0 to bit L)]. Meanwhile, the state of communication control unit 1 at a data receiving time is held in status register 5 and is transferred to circuit 4 (bit L+1 to bit M). Next, contents of circuit 4 are trasferred to relative address generation circuit 7 at the data receiving end to generate relative address 50 (where a bit addition part from bit N+1 to bit M is added), and this address 50 is transferred to the instructing relative address part at an address, which is determined previously, of unit 10 under the control of circuit 8, and simultaneously, interrupt 6 to CPU9 is caused, and the succeeding processing is transferred to software.
COPYRIGHT: (C)1980,JPO&Japio
JP13788278A 1978-11-10 1978-11-10 Communication control unit Pending JPS5566021A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13788278A JPS5566021A (en) 1978-11-10 1978-11-10 Communication control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13788278A JPS5566021A (en) 1978-11-10 1978-11-10 Communication control unit

Publications (1)

Publication Number Publication Date
JPS5566021A true JPS5566021A (en) 1980-05-19

Family

ID=15208883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13788278A Pending JPS5566021A (en) 1978-11-10 1978-11-10 Communication control unit

Country Status (1)

Country Link
JP (1) JPS5566021A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6137795A (en) * 1997-03-19 2000-10-24 Fujitsu Limited Cell switching method and cell exchange system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6137795A (en) * 1997-03-19 2000-10-24 Fujitsu Limited Cell switching method and cell exchange system

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