JPS5568726A - Oscillation preventing circuit for digital filter - Google Patents

Oscillation preventing circuit for digital filter

Info

Publication number
JPS5568726A
JPS5568726A JP14317978A JP14317978A JPS5568726A JP S5568726 A JPS5568726 A JP S5568726A JP 14317978 A JP14317978 A JP 14317978A JP 14317978 A JP14317978 A JP 14317978A JP S5568726 A JPS5568726 A JP S5568726A
Authority
JP
Japan
Prior art keywords
register
signal
output
digital
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14317978A
Other languages
Japanese (ja)
Other versions
JPS6139767B2 (en
Inventor
Masao Kasuga
Masaaki Sato
Takashi Matsushige
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP14317978A priority Critical patent/JPS5568726A/en
Priority to US06/095,554 priority patent/US4321685A/en
Publication of JPS5568726A publication Critical patent/JPS5568726A/en
Publication of JPS6139767B2 publication Critical patent/JPS6139767B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/04—Recursive filters
    • H03H17/0461—Quantisation; Rounding; Truncation; Overflow oscillations or limit cycles eliminating measures

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To prevent the oscillation caused when the overflow occurs for the device by holding the signal of the highest-rank bit among the output signals and at the same time feeding the other signals back to the input side of the device in the form of the normal complement display signal after the bit shifting. CONSTITUTION:The digital signal supplied from terminal 1 is held at register 2 and also supplied to multiplier 3 to be multiplied by the signal sent from ROM4. And the output is added in the digital way with the output given from register 6 at adder 5 and then sent to shift register 7 and register 8. In other words, the signal of the highest-rank bit is held at register 8 among the digital output signals of adder 5, and other signals undergo the bit shift at register 7. The output of registers 7 and 8 are supplied to register 9 and then turned into the digital signal of the complement display of normal 2 to be fed back to the input side of the device as well as to be delivered to the D/A converter. As a result, the oscillation can be prevented when the device has an overflow.
JP14317978A 1978-11-20 1978-11-20 Oscillation preventing circuit for digital filter Granted JPS5568726A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP14317978A JPS5568726A (en) 1978-11-20 1978-11-20 Oscillation preventing circuit for digital filter
US06/095,554 US4321685A (en) 1978-11-20 1979-11-19 Circuit for reducing the limit cycle in a digital filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14317978A JPS5568726A (en) 1978-11-20 1978-11-20 Oscillation preventing circuit for digital filter

Publications (2)

Publication Number Publication Date
JPS5568726A true JPS5568726A (en) 1980-05-23
JPS6139767B2 JPS6139767B2 (en) 1986-09-05

Family

ID=15332726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14317978A Granted JPS5568726A (en) 1978-11-20 1978-11-20 Oscillation preventing circuit for digital filter

Country Status (1)

Country Link
JP (1) JPS5568726A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63209209A (en) * 1987-02-25 1988-08-30 Yamaha Corp Digital signal processing circuit
US5984790A (en) * 1997-08-13 1999-11-16 Nsk Ltd. Universal joint

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63209209A (en) * 1987-02-25 1988-08-30 Yamaha Corp Digital signal processing circuit
US5984790A (en) * 1997-08-13 1999-11-16 Nsk Ltd. Universal joint

Also Published As

Publication number Publication date
JPS6139767B2 (en) 1986-09-05

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