JPS5731063A - Log storage circuit - Google Patents

Log storage circuit

Info

Publication number
JPS5731063A
JPS5731063A JP10592780A JP10592780A JPS5731063A JP S5731063 A JPS5731063 A JP S5731063A JP 10592780 A JP10592780 A JP 10592780A JP 10592780 A JP10592780 A JP 10592780A JP S5731063 A JPS5731063 A JP S5731063A
Authority
JP
Japan
Prior art keywords
input
gates
delaying
signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10592780A
Other languages
Japanese (ja)
Other versions
JPS6055853B2 (en
Inventor
Mitoo Fujino
Kazuyuki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55105927A priority Critical patent/JPS6055853B2/en
Publication of JPS5731063A publication Critical patent/JPS5731063A/en
Publication of JPS6055853B2 publication Critical patent/JPS6055853B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Abstract

PURPOSE:To obtain a detailed log record, by providing a switching circuit on the input side of a signal holding circuit, also utilizing the delaying circuits which have been connected in series, delaying an input signal little by little in order, and holding it. CONSTITUTION:Gates G1-G8 and a gate G9 consist of a NOR circuit, and an inverter, respectively, and to each one input of the gates G3, G5 and G7 are connected delaying circuits D1-D3, respectively. Outputs of registers R1-R4 are supplied to a memory M. In this case, input signals WD1-WD4 are supplied to the gates G2, G4, G6 and G8, and an input signal WD0 is sent to the delaying circuits D1-D3. Said input signals WD0-WD4 are computer internal state signals, and when a switching signal SEL is ''0'', transient phenomena of the input signal WD0 are stored in order of time series of each register R1-R4.
JP55105927A 1980-07-31 1980-07-31 History memory circuit Expired JPS6055853B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55105927A JPS6055853B2 (en) 1980-07-31 1980-07-31 History memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55105927A JPS6055853B2 (en) 1980-07-31 1980-07-31 History memory circuit

Publications (2)

Publication Number Publication Date
JPS5731063A true JPS5731063A (en) 1982-02-19
JPS6055853B2 JPS6055853B2 (en) 1985-12-06

Family

ID=14420483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55105927A Expired JPS6055853B2 (en) 1980-07-31 1980-07-31 History memory circuit

Country Status (1)

Country Link
JP (1) JPS6055853B2 (en)

Also Published As

Publication number Publication date
JPS6055853B2 (en) 1985-12-06

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