JPS55139697A - Test system for memory - Google Patents

Test system for memory

Info

Publication number
JPS55139697A
JPS55139697A JP4514579A JP4514579A JPS55139697A JP S55139697 A JPS55139697 A JP S55139697A JP 4514579 A JP4514579 A JP 4514579A JP 4514579 A JP4514579 A JP 4514579A JP S55139697 A JPS55139697 A JP S55139697A
Authority
JP
Japan
Prior art keywords
data
adc
cycles
cycle
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4514579A
Other languages
Japanese (ja)
Inventor
Takashi Ihi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4514579A priority Critical patent/JPS55139697A/en
Publication of JPS55139697A publication Critical patent/JPS55139697A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To make it possible to test a memory in a state close to actual use by applying respective data in continuous cycles and by regarding data in intermediate cycles as effective data.
CONSTITUTION: Inverters 25 and 26 invert address data modification signals ADC1 and ADC2 in "N-1"-th and "N+1"-th cycles. When signal ADC1 from NOR circuit 32 with input with NOT lowers in level through NAND circuits 28, 29 and 31, inversion data of address data ADD in the "N-1"-th cycle are generated and when ADC1 and ADC2 are both held at a high level, inversion address data in the "N"- th cycle are generated. Further, when signal ADC2 is low in level, inversion address data 5 in the "N+1"-th cycle are generated to apply a tested memory with data of continuous three cycles. In the "N"-th cycle, write data are validated by a chip- selective signal, write enable signal, etc., so that the memory can be tested in a state closed to actual use with influences of adjacent cycles added.
COPYRIGHT: (C)1980,JPO&Japio
JP4514579A 1979-04-13 1979-04-13 Test system for memory Pending JPS55139697A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4514579A JPS55139697A (en) 1979-04-13 1979-04-13 Test system for memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4514579A JPS55139697A (en) 1979-04-13 1979-04-13 Test system for memory

Publications (1)

Publication Number Publication Date
JPS55139697A true JPS55139697A (en) 1980-10-31

Family

ID=12711104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4514579A Pending JPS55139697A (en) 1979-04-13 1979-04-13 Test system for memory

Country Status (1)

Country Link
JP (1) JPS55139697A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5077690A (en) * 1989-08-09 1991-12-31 Atmel Corporation Memory input data test arrangement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5077690A (en) * 1989-08-09 1991-12-31 Atmel Corporation Memory input data test arrangement

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