JPS54102985A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS54102985A
JPS54102985A JP1020978A JP1020978A JPS54102985A JP S54102985 A JPS54102985 A JP S54102985A JP 1020978 A JP1020978 A JP 1020978A JP 1020978 A JP1020978 A JP 1020978A JP S54102985 A JPS54102985 A JP S54102985A
Authority
JP
Japan
Prior art keywords
circuit
gate
push
parallel
output driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1020978A
Other languages
Japanese (ja)
Inventor
Osamu Tomizawa
Kenji Anami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1020978A priority Critical patent/JPS54102985A/en
Publication of JPS54102985A publication Critical patent/JPS54102985A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE: To decrease the number of the step of the output driving circuit and thus to reduce the delay time for the master sliding system IC containing the gate array by connecting in parallel two units of the final step gate of the IC internal logic circuit which is connected to the input terminal of the output driving circuit.
CONSTITUTION: Output driving circuit 110 consists of the push-pull circuit using the MOS transistor and the inverter, and the gate to be connected to input terminal 101 of circuit 110 is composed of the parallel circuit of logic gate 109a and 109b. And the signal featuring the opposite phase to the input signal is produced at output terminal 102. Thus, two units of the gate are put in parallel to cause no difference from the conventional constitution for the push-pull circuit comprising enhancement- type MOS transistor 105 and 106 to be provided to circuit 110. But only one unit of inverter 108 suffices for the preamplifier which is connected to the push-pull circuit. As a result, the number of the step can be decreased with the reduced delay time.
COPYRIGHT: (C)1979,JPO&Japio
JP1020978A 1978-01-31 1978-01-31 Semiconductor integrated circuit Pending JPS54102985A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1020978A JPS54102985A (en) 1978-01-31 1978-01-31 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1020978A JPS54102985A (en) 1978-01-31 1978-01-31 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS54102985A true JPS54102985A (en) 1979-08-13

Family

ID=11743873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1020978A Pending JPS54102985A (en) 1978-01-31 1978-01-31 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS54102985A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958840A (en) * 1982-09-28 1984-04-04 Mitsubishi Electric Corp Complementary mos gate array type semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958840A (en) * 1982-09-28 1984-04-04 Mitsubishi Electric Corp Complementary mos gate array type semiconductor integrated circuit device

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