JPH01106105A - Sequence controller - Google Patents

Abstract

PURPOSE:To obtain an input signal having the pulse width smaller than the time of a single scan by a simple means by using a designation register means which records the pulse signals having the pulse width smaller than the single scan time to an input designation memory. CONSTITUTION:An arithmetic processing means 3 obtains an input signal via an input interface 2 and produces a load control signal based on a sequence control program to give it to an output interface 4. A designation register means 6 records the pulse signal having the pulse width smaller than the time of a single scan to an input designation memory 5a via input ports I1, I2.... Then a signal state storage means 7 records the record data to a state memory 5b after reading it out the memory 5a during the fixed time interruption processing carried out with the fixed scan time. Then the means 3 puts the data read out of the memory 5b into an internal input memory 5c for execution of the input/output processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a sequence controller that controls a load based on a sequence control program.

[Background Art] Conventionally, this type of sequence controller has a program memory that stores a sequence control program, input signals input to an input port via an input interface, and outputs a load control signal based on the sequence control program. It is composed of an arithmetic processing means that is created and outputted through an output port and an output interface, and the arithmetic processing means performs signal input/output processing, sequence control program execution processing, and peripheral device path J! ! ! (Data communication (ff) with programming equipment, etc. was performed in order. Here, a fixed time interval during which processing such as signal input/output processing is performed is called one scan time, and this one scan time A method of inputting and outputting signals at a rate of one time is called a refresh method.In such a refresh method, the input signal is a pulse signal with a pulse width shorter than one scan time (for example, an output signal from a sensor, etc.). )
When the input signal is input, the input signal cannot be reliably captured, so there is a problem in that the sequence control operation cannot be performed based on the sensor output. Therefore, as a method to reliably capture sensor outputs with such short pulse widths, there is a method to use multiple sensors so that an output signal is always obtained from one of the sensors during input/output processing. A method of making the pulse width of the output signal wider than one scan time using a special sensor that can vary the pulse width of the sensor output through a special dedicated unit for changing the pulse width of the sensor output. There are methods to input the data into the sequence controller, but each method requires multiple sensors, special sensors,
There is a problem in that a dedicated unit is required, which complicates the configuration and increases costs.

``Object of the Invention J The present invention has been made in view of the above points, and its object is to be able to perform sequence control operations based on an input signal with a pulse width shorter than one scan time. Moreover, it is an object of the present invention to provide a sequence controller that has a simple configuration and is low in cost.

[Disclosure of the Invention] (Structure) The present invention incorporates a program memory that stores a sequence control program and an input signal that is input to an input port via an input interface, and generates a load control signal based on the sequence control program. It is composed of an arithmetic processing means that is created and output through an output port and an output interface, and the arithmetic processing means sequentially performs signal input/output processing, sequence control program execution processing, and peripheral device processing. In a sequence controller that performs signal input/output at a rate of once per scan time, specify an input port that can accept a pulse signal with a pulse width shorter than one scan time and record it in the input specification memory. and a designated registration means for reading out, via an input interface, the state of the input signal input to the input port designated by the designated registration means during scheduled interrupt processing executed at a constant scan time and storing it in a state memory. The data read from the state memory during input/output processing is transferred to the internal input memory of the arithmetic processing means to capture the input signal state, so that the pulse is shorter than one scan time. The present invention provides a sequence controller that can perform sequence control operations based on a wide input signal, has a simple configuration, and is inexpensive.

(Embodiment) FIG. 1 shows an embodiment of the present invention, which includes a program memory 1 for storing a sequence control program, and an input port via an input interface 2.1. , I2...
..., and creates a load control signal based on the sequence control program. , O□... and an arithmetic processing means 3 that outputs via an output interface 4,
As shown in FIG. 3, the arithmetic processing means 3 sequentially performs signal input/output processing, sequence control program execution processing, and peripheral device processing, and also performs one scan set by basic time measurement processing. In a sequence controller similar to the conventional example that inputs and outputs signals at a rate of once per hour, an input capo that can accept pulse signals with a pulse width shorter than one scan time, I,
, L..., and records it in the input designation memory 5-a, and the input designated by the designation registration means 6 during the regular interrupt processing executed at a constant scan time. A signal state storage means 7 is provided to read the state of the input signal input to the capo) I+-It through the input interface 71 chair 2 and store it in the state memory 5b. The data read out from the state memory 5b is transferred to the internal input memory 5c of the arithmetic processing means 3.
The input signal status is captured by transferring the input signal to the input signal. FIG. 2 shows the hardware configuration of the embodiment, which includes an internal input memory 5c for calculations and performs various calculation processes.
PUl0, an interrupt signal generating section 11 that generates a timing signal for a timer interrupt, a ROM 12 that stores a system program, and an input capacitor) I,, I2, etc.
・I10 forming output port 0□02...
Port 13, program memory 1, input specification memory 5
a, a RAM 14 forming a state memory 5b, etc., and an input/output interface 7215.

The operation of the embodiment will be specifically explained below.

Figure 4 shows an input port (If) where a pulse signal with a pulse width shorter than one scan time is input in peripheral device processing.
, I2... is a 70-chart when specifying . A determination process (4-2) is performed to check whether it is a designated command (registration command). Here, if it is a registration command, its contents are recorded in the input designation memory 5a. FIG. 5 shows the state of the input designation memo '75a at this time, where the number n of input points for pulse signal input is recorded at the first address (5-1), and the number n of input points for pulse signal input is recorded at the first address (5-1), and
-2) (5-3)... Actual input port designation data (input port number) is recorded. In addition,
Although the number of input points, 1, can be set arbitrarily, in the following explanation, n=1 (only 1 point specified) will be explained.

Figure 6 shows a fixed scan time (
This is a 70-chart showing the periodic interrupt processing that is normally performed at 1 to several m5 eq). Basic time measurement processing similar to the conventional one such as system clock counting processing is performed, and then the input designation memory 5a ( Check the contents of s-i) and if n is not 0, input capo-)1t-I2...
. . are read from the input designation memory 5a, and the input signal states are recorded in the read state memory 5b via the input interface 2. In this case, read processing (
6-3) is the first readout to prevent noise signals from being read out by mistake, and in the subsequent readout process (6-4), the input signal state is read out again, and the results of both readout processes are The input signal state is determined by taking the logical AND of . That is, when both read processing results are 1, it is assumed that there is an input signal, and when either one is 0, it is assumed that there is no input signal, thereby preventing malfunctions due to noise signals.

The input signal state read out as described above is temporarily stored in the state memory 5b (7-2
) is recorded. Further, in the process (6-5), the exclusive OR of the result and the sampling value (7-3) of the input signal in the previous interrupt process at a fixed time interval is performed, and the result is used in the state memory 5b. i with the content of (7-2)
! If one is filled in, it becomes possible to detect the rising state of the pulse signal. The reason for detecting the rising edge of the pulse signal is to prevent continuous signals from being erroneously recorded as pulse signals.
-4) and the result is the state memory (7-
4). In this case, the reason for performing the logical sum is to prevent bits other than (7-4) of the state memory 5b (that is, other pulse inputs) from being erased. R
Later, the content recorded in the memory (7-2) and the previous sampling value are copied to (7-3) of the state memory 5b in preparation for the next process.

Through the above processing, a pulse signal can be captured.

Next, FIG. 8 is a flowchart showing the input/output process during the input/output process, and after the input refresh is completed,
Check the contents of (5-1) in the input setting memory 5a and find that n is 0.
If not, the data indicating the input signal state is read from (7-4) of the status memo 1Jsb and the specified input signal is stored in the internal human memory 5c of the arithmetic processing means.
Calculate the address corresponding to , and calculate the contents of that address (7
-4) and the result is stored in the internal input memory 5.
Store it at the corresponding address of c. Through this process, the pulse signal state taken in during the interrupt process is written to the internal input memory 5C shown in FIG. It is now possible to output. Furthermore, after this, state memo 1.15
The contents of (7-4) in b are cleared to prepare for capturing the pulse signal during interrupt processing of the next scan.

Fig. 10 shows how the input signal is actually taken into the internal input memory 5c through the above processing, and Fig. 10 (a) shows the pulse width (scan time, period) of scan time x 2. The figure (b) shows a case where the timing overlaps with the Ilo paste fresh processing under the same conditions as the pattern in the figure (,). In addition, FIG. 6(e) shows a case where a normal signal (pulse width>scan time) is input, and FIG. 10(d) shows a case where period=scan time. Furthermore, FIG. 6(e) shows a case where a plurality of pulse signals are input within one scan time.

We can think of all possible patterns in the above five examples, and in any case, the pulse signal is input to input ports I, I2, etc. that are specified so that they can be input. Since the pulse signal is reliably captured into the internal human power memory 5c of the processing unit Fi3 via the status memo 1j5b with a delay of one scan time at most, the corresponding load control signal can be output by the sequence control program. .

Also, in the case of normal signals, the same sequence control operation as in the conventional example is performed, so the input ports (I, I2, etc.) specified to correspond to the pulse signal input are There is no problem even if the signal is received.

[Effect of the Invention 1] As described above, the present invention captures an input signal input to an input port via an input interface, and
It consists of an arithmetic processing means that creates a load control signal based on a sequence control program and outputs it through an output port and an output interface.The arithmetic processing means performs signal input/output processing and execution processing of the sequence control program. In a sequence controller that sequentially performs peripheral device processing and performs signal input/output at a rate of once per scan time, an input that can accept pulse signals with a pulse width shorter than one scan time. A designated registration means that specifies a port and records it in the input designated memory, and an input interface that records the state of the input signal input to the input port designated by the designated registration means during the periodic interrupt processing that is executed at a fixed scan time. A signal state storage means is provided to read the data through the interface and store it in the state memory, and at the time of input/output processing, the data read from the state memory is transferred to the internal input memory of the arithmetic processing means to capture the input signal state. As a result, it is possible to perform a sequence control operation based on an input signal having a pulse width shorter than one scan time, and it is also possible to provide a sequence controller that is simple in structure and inexpensive.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block circuit diagram showing a specific configuration of the same, and FIGS. 3 to 10 are operation explanatory diagrams of the same. 1 is program memory, 2 is input interface, 3
4 is an arithmetic processing means, 4 is an output interface 7, 5a is an input designation memory, 51] is a state memory, 5c is an internal input memory, 6 is a designation registration means, and 7 is a signal state storage means. Agent Patent Attorney Ishi 1) Ai 7th 1st Illustrated Book ba 5b Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] (1) A program memory that stores a sequence control program and an input signal that is input to an input port via an input interface, creates a load control signal based on the sequence control program, and outputs it via an output port and an output interface. The arithmetic processing means sequentially performs signal input/output processing, sequence control program execution processing, and peripheral device processing, and performs output processing once per scan time. In a sequence controller configured to input and output signals, there is provided a designation registration means for designating an input port capable of receiving a pulse signal having a pulse width shorter than one scan time and recording it in an input designation memory, and a specified scan time. and signal state storage means for reading the state of the input signal input to the input port designated by the designated registration means during the regular interrupt processing executed by the input interface, and storing the state in the state memory. A sequence controller characterized in that during output processing, data read from the state memory is transferred to an internal input memory of an arithmetic processing means to capture an input signal state.