JPS56111955A - Shared memory control method of multicpu system - Google Patents

Shared memory control method of multicpu system

Info

Publication number
JPS56111955A
JPS56111955A JP1506780A JP1506780A JPS56111955A JP S56111955 A JPS56111955 A JP S56111955A JP 1506780 A JP1506780 A JP 1506780A JP 1506780 A JP1506780 A JP 1506780A JP S56111955 A JPS56111955 A JP S56111955A
Authority
JP
Japan
Prior art keywords
access
cpu2
cpu1
area
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1506780A
Other languages
Japanese (ja)
Inventor
Norio Yokouchi
Isao Takanishi
Hiroki Nishinaka
Katsuo Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Zosen Corp
Original Assignee
Hitachi Zosen Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Zosen Corp filed Critical Hitachi Zosen Corp
Priority to JP1506780A priority Critical patent/JPS56111955A/en
Publication of JPS56111955A publication Critical patent/JPS56111955A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To secure an access right of a shared memory to both the main and secondary CPUs without discontinuing the operation of the CPU, by using both an access permission interruption and an access abandon interruption. CONSTITUTION:A shared memory 3 is installed between the main CPU1 and the secondary CPU2 to secure an asynchronous read/write for these CPUs. The access right of the shared data area 5 of the memory 3 is usually given to the CPU1. Then the access permission interruption 7 is given to the CPU2 from the CPU1 in case the CPU1 gives no access to the area 5 and at the same time the CPU2 gives an access request to the area 5 with an identification secured for setting of the access request flag 6 of the memory 3. The CPU2 resets the flag 6 and at the same time gives an access to the area 5. Then an access abandon interruption 8 is given to the CPU2 when the process is completed. Thus the access right of the area 5 is transferred to the CPU1.
JP1506780A 1980-02-08 1980-02-08 Shared memory control method of multicpu system Pending JPS56111955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1506780A JPS56111955A (en) 1980-02-08 1980-02-08 Shared memory control method of multicpu system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1506780A JPS56111955A (en) 1980-02-08 1980-02-08 Shared memory control method of multicpu system

Publications (1)

Publication Number Publication Date
JPS56111955A true JPS56111955A (en) 1981-09-04

Family

ID=11878493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1506780A Pending JPS56111955A (en) 1980-02-08 1980-02-08 Shared memory control method of multicpu system

Country Status (1)

Country Link
JP (1) JPS56111955A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010262431A (en) * 2009-05-01 2010-11-18 Fuji Electric Fa Components & Systems Co Ltd Access method of and access control device for dual port memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010262431A (en) * 2009-05-01 2010-11-18 Fuji Electric Fa Components & Systems Co Ltd Access method of and access control device for dual port memory

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