JPS54156433A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS54156433A
JPS54156433A JP6515378A JP6515378A JPS54156433A JP S54156433 A JPS54156433 A JP S54156433A JP 6515378 A JP6515378 A JP 6515378A JP 6515378 A JP6515378 A JP 6515378A JP S54156433 A JPS54156433 A JP S54156433A
Authority
JP
Japan
Prior art keywords
information
buffer memory
memory
circuit
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6515378A
Other languages
Japanese (ja)
Other versions
JPS5922979B2 (en
Inventor
Yoshio Hirota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53065153A priority Critical patent/JPS5922979B2/en
Publication of JPS54156433A publication Critical patent/JPS54156433A/en
Publication of JPS5922979B2 publication Critical patent/JPS5922979B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To enable to establish greater capacity with less number in the circuit elements, by using RAM for the buffer memory and discriminating the propriety of the information exchange among units through the control of no-passing with the buffer memory control circuit.
CONSTITUTION: To feed information between the units 1 and 2, the information is fed to the buffer memory 3 and also to the response control circuits 4 and 5. RAM is used as the memory 3. The counters 6 and 7 give adderss to the memory 3, 1 only adds with one information exchange, FF circuits 8 and 9 are inverted with overflow, and the output is fed to the buffer memory control circuit 10. Assuming that the information is transferred from the unit 2 to 1, the information is transferred from the unit 2 to the memory 3. Simultaneously, request is made to sore the information of the unit 2 to the memory 3, for the circuit 10 through the circuit 5. The circuit 10 performs comparison of the output of the counters 6 and 7 and FF 8,9, to discriminate the permission, waiting and failure of the information exchange with the control of no-passing.
COPYRIGHT: (C)1979,JPO&Japio
JP53065153A 1978-05-31 1978-05-31 Buffer memory control method Expired JPS5922979B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53065153A JPS5922979B2 (en) 1978-05-31 1978-05-31 Buffer memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53065153A JPS5922979B2 (en) 1978-05-31 1978-05-31 Buffer memory control method

Publications (2)

Publication Number Publication Date
JPS54156433A true JPS54156433A (en) 1979-12-10
JPS5922979B2 JPS5922979B2 (en) 1984-05-30

Family

ID=13278643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53065153A Expired JPS5922979B2 (en) 1978-05-31 1978-05-31 Buffer memory control method

Country Status (1)

Country Link
JP (1) JPS5922979B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60192040U (en) * 1984-05-25 1985-12-20 沖電気工業株式会社 Control processing unit for input/output devices
JPS6429926A (en) * 1987-07-24 1989-01-31 Matsushita Electric Ind Co Ltd Fifo circuit
JPH077327B2 (en) * 1991-02-19 1995-01-30 インターナショナル・ビジネス・マシーンズ・コーポレーション Data transfer method
WO2000079378A1 (en) * 1999-06-22 2000-12-28 Seiko Epson Corporation First-in first-out storage device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344247Y2 (en) * 1986-03-31 1991-09-18

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60192040U (en) * 1984-05-25 1985-12-20 沖電気工業株式会社 Control processing unit for input/output devices
JPS6429926A (en) * 1987-07-24 1989-01-31 Matsushita Electric Ind Co Ltd Fifo circuit
JPH077327B2 (en) * 1991-02-19 1995-01-30 インターナショナル・ビジネス・マシーンズ・コーポレーション Data transfer method
WO2000079378A1 (en) * 1999-06-22 2000-12-28 Seiko Epson Corporation First-in first-out storage device
US6772280B1 (en) 1999-06-22 2004-08-03 Seiko Epson Corporation First-in first-out storage device

Also Published As

Publication number Publication date
JPS5922979B2 (en) 1984-05-30

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