JPS5750037A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS5750037A
JPS5750037A JP55125838A JP12583880A JPS5750037A JP S5750037 A JPS5750037 A JP S5750037A JP 55125838 A JP55125838 A JP 55125838A JP 12583880 A JP12583880 A JP 12583880A JP S5750037 A JPS5750037 A JP S5750037A
Authority
JP
Japan
Prior art keywords
common memory
data
bus
bus line
cpuii
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55125838A
Other languages
Japanese (ja)
Inventor
Toru Taniguchi
Shigeru Nakamura
Masaaki Kurata
Shinichi Tomizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55125838A priority Critical patent/JPS5750037A/en
Publication of JPS5750037A publication Critical patent/JPS5750037A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Abstract

PURPOSE:To reduce a circuit scale and to shorten a data transfer time, by connecting a bus extending to a common memory provided on a composite microprocessor system, to a bus changeover switch, and using the common memory, inhibiting a double connection. CONSTITUTION:In a system consisting of plural microprocessors (CPU), for instance, in case when a data is transferred to the right side CPUII from the left side CPUI, a bus line 5 and a common memory bus line 7 are connected by a common memory use request register 4, a changeover deciding part 3 for deciding a common memory use state, and a bus chageover switch 2, through various signal lines, and the data is transferred to a common memory 1. When the CPUI requests a data analysis to the CPUII, a bus line 6 and the common memory bus line 7 are connected by the same procedure as said one, and a data in the common memory 1 is transferred to the CPUII.
JP55125838A 1980-09-10 1980-09-10 Data transfer system Pending JPS5750037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55125838A JPS5750037A (en) 1980-09-10 1980-09-10 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55125838A JPS5750037A (en) 1980-09-10 1980-09-10 Data transfer system

Publications (1)

Publication Number Publication Date
JPS5750037A true JPS5750037A (en) 1982-03-24

Family

ID=14920186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55125838A Pending JPS5750037A (en) 1980-09-10 1980-09-10 Data transfer system

Country Status (1)

Country Link
JP (1) JPS5750037A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136853A (en) * 1983-12-26 1985-07-20 Fujitsu Ltd Data transfer system
JPS6241699U (en) * 1985-08-30 1987-03-12
JPS62174855A (en) * 1986-01-28 1987-07-31 Nec Corp Bus switching method
JPS63213298A (en) * 1987-02-27 1988-09-06 Shimadzu Corp X-ray cinematographic equipment
JPS63237154A (en) * 1987-03-26 1988-10-03 Asia Electron Kk Memory access system
US4866597A (en) * 1984-04-26 1989-09-12 Kabushiki Kaisha Toshiba Multiprocessor system and control method therefor
US6275875B1 (en) 1991-04-15 2001-08-14 Canon Kabushiki Kaisha Electronic apparatus with version-up information having address information storing in EEPROM
JP2012108886A (en) * 2010-11-16 2012-06-07 Micron Technology Inc Multi-channel memory with embedded channel selection

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136853A (en) * 1983-12-26 1985-07-20 Fujitsu Ltd Data transfer system
US4866597A (en) * 1984-04-26 1989-09-12 Kabushiki Kaisha Toshiba Multiprocessor system and control method therefor
JPS6241699U (en) * 1985-08-30 1987-03-12
JPS62174855A (en) * 1986-01-28 1987-07-31 Nec Corp Bus switching method
JPS63213298A (en) * 1987-02-27 1988-09-06 Shimadzu Corp X-ray cinematographic equipment
JPS63237154A (en) * 1987-03-26 1988-10-03 Asia Electron Kk Memory access system
US6275875B1 (en) 1991-04-15 2001-08-14 Canon Kabushiki Kaisha Electronic apparatus with version-up information having address information storing in EEPROM
JP2012108886A (en) * 2010-11-16 2012-06-07 Micron Technology Inc Multi-channel memory with embedded channel selection

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