JPS5515525A - Signal transmission system of memory system - Google Patents

Signal transmission system of memory system

Info

Publication number
JPS5515525A
JPS5515525A JP8737978A JP8737978A JPS5515525A JP S5515525 A JPS5515525 A JP S5515525A JP 8737978 A JP8737978 A JP 8737978A JP 8737978 A JP8737978 A JP 8737978A JP S5515525 A JPS5515525 A JP S5515525A
Authority
JP
Japan
Prior art keywords
signal
signal line
request
signals
request acceptance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8737978A
Other languages
Japanese (ja)
Inventor
Kunihiro Koyabu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8737978A priority Critical patent/JPS5515525A/en
Publication of JPS5515525A publication Critical patent/JPS5515525A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve economy by reducing signal line and signal receiver circuits at a CPU side in number by using bus connection lines among memory units for signals lines sending out request acceptance signals.
CONSTITUTION: Momory units MM are connected via a bus and request acceptance signal line 3 connecting to CPU and CC is provided. When a normal write-read operation is requested from CC via operation request signal line 2, one of memory units MM0 to MMn operates by address information sent out from signal line group 1 and one of request acceptance signals (b0) to (bn) equivalent to operating MM is sent out to signal line 3 with level "O". At the time of refresh operation, on the other hand, signals (bo) to (bn) become level "O" at the same time and are sent onto signal line 3. Through wired-OR, request acceptance signal C is obtained and CC confirms that signal C becomes level "O", namely, the request is accepted, thereby sending out the next operation request. Consequently, only one receiver circuit is required which receives signal (c) of CC and only one line is used which sends signal (c) out.
COPYRIGHT: (C)1980,JPO&Japio
JP8737978A 1978-07-17 1978-07-17 Signal transmission system of memory system Pending JPS5515525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8737978A JPS5515525A (en) 1978-07-17 1978-07-17 Signal transmission system of memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8737978A JPS5515525A (en) 1978-07-17 1978-07-17 Signal transmission system of memory system

Publications (1)

Publication Number Publication Date
JPS5515525A true JPS5515525A (en) 1980-02-02

Family

ID=13913254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8737978A Pending JPS5515525A (en) 1978-07-17 1978-07-17 Signal transmission system of memory system

Country Status (1)

Country Link
JP (1) JPS5515525A (en)

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