JPS5652431A - Bus request control system - Google Patents

Bus request control system

Info

Publication number
JPS5652431A
JPS5652431A JP12839979A JP12839979A JPS5652431A JP S5652431 A JPS5652431 A JP S5652431A JP 12839979 A JP12839979 A JP 12839979A JP 12839979 A JP12839979 A JP 12839979A JP S5652431 A JPS5652431 A JP S5652431A
Authority
JP
Japan
Prior art keywords
signal
brq
bus
bus request
units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12839979A
Other languages
Japanese (ja)
Inventor
Hiroto Katsumata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12839979A priority Critical patent/JPS5652431A/en
Publication of JPS5652431A publication Critical patent/JPS5652431A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To use a bus more efficiently, by sending out the first and second bus request signals to the first and second two-way signal lines from the bus request conrol unit provided on each I/O, and outputting a bus approval signal from CPU by being based on the said signal.
CONSTITUTION: CPU1, the main memories 21, 22 and I/Os 31W3n are connected in common, respectively, and the bus request control units 71W7n are provided on I/Os 31W3n, respectively. The units 71W7n outputs a signal BRQ1 only in case there is no bus request signal BRQ1 on the two-way signal line 5 when a bus request has occurred in the corresponding I/O. Also, the units 71W7n output a bus request signal BRQ2 to the two-way signal line when a bus request has occurred in the units 31W3n. CPU1 outputs a bus approval signal BACK showing the bus occupancy permission based on the signals BRQ1, BRQ2, outputs the signals BRQ1, BRQ2, and only the I/O which has received the signal BACK is able to occupy the bus. In this regard, I/O responds to the signal BACK, stops the signal BRQ2, and stops the signal BRQ1 when transfer of a data has been finished.
COPYRIGHT: (C)1981,JPO&Japio
JP12839979A 1979-10-04 1979-10-04 Bus request control system Pending JPS5652431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12839979A JPS5652431A (en) 1979-10-04 1979-10-04 Bus request control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12839979A JPS5652431A (en) 1979-10-04 1979-10-04 Bus request control system

Publications (1)

Publication Number Publication Date
JPS5652431A true JPS5652431A (en) 1981-05-11

Family

ID=14983831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12839979A Pending JPS5652431A (en) 1979-10-04 1979-10-04 Bus request control system

Country Status (1)

Country Link
JP (1) JPS5652431A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61199153A (en) * 1985-02-28 1986-09-03 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Bus arbiter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61199153A (en) * 1985-02-28 1986-09-03 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Bus arbiter
JPH0462098B2 (en) * 1985-02-28 1992-10-05 Intaanashonaru Bijinesu Mashiinzu Corp

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