JPS5465446A - Direct memory access control system - Google Patents

Direct memory access control system

Info

Publication number
JPS5465446A
JPS5465446A JP13231877A JP13231877A JPS5465446A JP S5465446 A JPS5465446 A JP S5465446A JP 13231877 A JP13231877 A JP 13231877A JP 13231877 A JP13231877 A JP 13231877A JP S5465446 A JPS5465446 A JP S5465446A
Authority
JP
Japan
Prior art keywords
dma
signal
circuit
synchronization
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13231877A
Other languages
Japanese (ja)
Other versions
JPS581811B2 (en
Inventor
Yoichi Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52132318A priority Critical patent/JPS581811B2/en
Publication of JPS5465446A publication Critical patent/JPS5465446A/en
Publication of JPS581811B2 publication Critical patent/JPS581811B2/en
Expired legal-status Critical Current

Links

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  • Bus Control (AREA)

Abstract

PURPOSE: To facilitate the laying of the transfer line as well as to increase the using efficiency effectively for the common bus by securing an one-after-another connectio n for the DMA request signal transfer lines and also carrying out the DMA data transfer immediately in synchronization with the system clock.
CONSTITUTION: The DMA request signal Q transfer line 5 is provided in an one- after-another way between input/output control units 2-lW2-n and DMA control circuit 4, along with system clock generating source 7 and DMA process sunits 8-lW8-n. The higher priority is given to the more distant unit from circuit 4 through line 5 for the DMA request via units 2-lW2-n. In other words, unit 2-(n-1), for example, is passed through directly toward circuit 4 if signal Q is given from the right-side unit, and circuit 4 generates the DMA permission signal (signal ×DAA in logic 0) onto line 6 in synchronization with the DMA data transfer period when signal Q is deteced (signal ×DAR in logic 0). Thus, the DMA data transfer is carried out immediately in synchronization with clock 7.
COPYRIGHT: (C)1979,JPO&Japio
JP52132318A 1977-11-04 1977-11-04 Direct memory access control method Expired JPS581811B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52132318A JPS581811B2 (en) 1977-11-04 1977-11-04 Direct memory access control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52132318A JPS581811B2 (en) 1977-11-04 1977-11-04 Direct memory access control method

Publications (2)

Publication Number Publication Date
JPS5465446A true JPS5465446A (en) 1979-05-26
JPS581811B2 JPS581811B2 (en) 1983-01-13

Family

ID=15078499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52132318A Expired JPS581811B2 (en) 1977-11-04 1977-11-04 Direct memory access control method

Country Status (1)

Country Link
JP (1) JPS581811B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621223A (en) * 1979-07-30 1981-02-27 Ibm Cycle steal mechanism

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50137636A (en) * 1974-04-22 1975-10-31

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50137636A (en) * 1974-04-22 1975-10-31

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621223A (en) * 1979-07-30 1981-02-27 Ibm Cycle steal mechanism
JPS5820061B2 (en) * 1979-07-30 1983-04-21 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション cycle steel mechanism

Also Published As

Publication number Publication date
JPS581811B2 (en) 1983-01-13

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