JPS581811B2 - Direct memory access control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides direct memory. Access control systems, particularly in data processing systems in which a plurality of input/output control devices and a central processing unit consisting of a microprocessor, for example, are connected on a common bus, are used to control access control directly between the individual output control devices. memory. Direct by creating an access request signal transfer line. The memory access control device is the direct one mentioned above. memory. In addition to managing access requests, one of the plurality of input/output control devices is controlled by a direct memory access permission signal that is issued in synchronization with a predetermined period during the ICPU cycle period that the direct memory access control device has permitted. That is direct. The present invention relates to a direct memory access control method that performs data transfer in response to memory access requests.

Conventionally, in a data processing system using a microprocessor, for example, a plurality of human output control devices and the microprocessor are connected on a common bus.

One of the above input/output control devices is direct. When data is transferred between the main storage device and the main storage device by memory access (hereinafter abbreviated as DMA), the DMA control device manages the DMA request signal issued by the input/output control device and quickly transfers the data based on the DMA request signal. be allowed.

However, for the DMA control, it is only necessary to perform DMA data transfer in response to an input/output control device that requires data transfer corresponding to a DMA request (hereinafter referred to as DMA data transfer). DMA request signal transfer lines are provided in a radial pattern, that is, in a kite-like pattern, between a plurality of input/output control devices requiring the above-mentioned DMA control device and the DMA control device.

However, when designing the entire data processing system, instead of designing a system that deals with each system one by one according to user requests, it is necessary to modularize the system and design it in advance so that it can deal with each type of system. has become desired.

For this reason, all the input/output devices provided in the system must perform DMA data transfer, which brings about many difficulties in the conventional method of providing a signal transfer line using a telegraph signal transfer line.

In addition, in the case of conventional transfer control, it is necessary to perform C communication until the DMA data transfer is actually performed when a DMA request is issued, which is also difficult in terms of using a common bus.The present invention solves the above problems. In order to do this, we have noticed that the access of the main memory has recently become more frequent and the clock is starting to lag during the IC CPU cycle period, so we created a DMA data transfer period within the cycle period and synchronized it with the system clock. For this purpose, the direct access control method of the present invention provides a connection input/output control device, a main storage device, and an intermediate device on a common bus, so that each of the above-mentioned plurality of input/output controls can be mixed. The access control circuit is connected to the data processing system in which the processing units transfer data using the common bus. memory. There is no space between the access control and the input/output control device. memory. In addition to transferring the access request signal, it is also diverted in a branch connection type. Connect the access permission signal line to the memory. The access control circuit uses direct memory access request signals transferred by the converter. When a request signal is detected, the ICPU directly executes the command in synchronization with a predetermined processing period of the central processing unit. The input/output control device configured to issue a memory enable signal to the direct memory signal line is configured such that no other input/output control device that is superior to the input/output control device has issued the direct access request signal and the input/output control device is configured to issue the direct memory access request signal to the direct memory signal line. Subject to the request signal k, the above-mentioned direct mail { direct. a memo processing unit, and during the existence of the direct access permission signal, the direct. memory. The feature is that data transfer is performed in response to access requests.

This will be explained below with reference to the drawings. FIG. 1 is an explanatory diagram explaining the problems of the conventional method. FIG. 2 is an explanatory diagram explaining the mode of accessing the main memory. FIG. 3 is the configuration of an embodiment of the present invention. DMA for human output control equipment
Embodiment configuration of the processing unit, FIG. 5 is D shown in FIG.
A time chart illustrating the operation of the MA processing unit is shown.

In FIG. 1, 1 is a microprocessor, 2-1 to 2-n are input/output control devices, 3 is a common bus, and 4 is a D
MA control circuit, 5 DMA request signal transfer line, 6 D
Indicate the MA permission signal line.

Conventionally, for example, in the case of a data processing system using a microprocessor, the microprocessor 1 and a plurality of input/output control devices 2-1 to 2-n are connected to a common bus 3, and one device uses the common bus 3. Data transfer is performed while occupying the space.

When one input/output control device, for example 2-1, transfers data between it and the main memory (input/output control device 2-n) using DMA, a cycle is inserted between data transfers by the microprocessor 1. ．． DMA7 overnight transfer is performed by steal.

That is, the input/output control device 2-1 uses the DMA via line 5.
The request signal is sent to the DMA control circuit 4, and the DMA control circuit 4 receives the DMA request signal and interrupts the microprocessor 1.

Then, the DMA control circuit 4 sends a DMA permission signal to the input/output control device #2-1 via the line 6, and thereafter performs necessary communications to perform DMA data transfer.

Further, in the case of a conventional data processing system, not all input/output control devices in a given system perform DMA data transfer, but only some input/output control devices in the system perform DMA data transfer.

That is, the lines 5 and 6 are wired in correspondence with the input/output control device that performs DMA data transfer.

However, as stated at the beginning of this specification, instead of a design that deals with individual systems specified by the user, a design that modularizes the system so that it can easily deal with various systems will be adopted. As shown in FIG. 1, connecting the DMA request signal transfer line 5 to all input/output control devices in a single-handed manner causes many difficulties in wiring.

In addition, in order to actually transfer DMA data overnight, it is necessary to organize the DMA requests that occur in Ranta Hiro and synchronize them with the system clock, and many A communication procedure is required, and there are also problems in terms of effective use of the common bus 3.

On the other hand, recently the access time of main memory has been shortened,
It is no longer necessary to use the entire existing ICPU cycle to access the main memory, and so to speak, a time margin is created within the ICPU cycle.

That is, FIG. 2 explains this point, and even if address information is issued on the common bus 3 after approximately half of the ICPU cycle period has elapsed, the read data will not be read from the main memory at the end of the ICPU cycle period. is read or written immediately before the corresponding ICPU cycle period. Even if data is given, it can be written to the main memory.

In consideration of the above points, the present invention connects the DMA request signal transfer line in a so-called "Imosu" style to facilitate the wiring of the above line to each input/output control device, and also connects the DMA request signal transfer line to the ICPU as shown in FIG. The first half of the cycle should be actively utilized.The DMA data transfer period allows DMA data transfer to be performed immediately in synchronization with the system clock within the above period without omitting many communications.

FIG. 3 shows an embodiment of the present invention.

Codes in the figure: 1.2-1 to 2-n, 3, 4, 5, 6
corresponds to Figure 1, and 7 is the system. Represents the clock source.

Further, 8-i to 8-n represent the main DMA processing units.

In the case of the present invention, a similar type of DMA request signal transfer line 5 is provided between each of the input/output control devices 2-1 to 2-n and the DMA control circuit 4 as described above.

Each input/output control device 2 has a DMA processing unit 8, and each input/output control device 2-1 to 2-n has a DMA processing unit 8.
In the case shown in the figure, the input/output control device located farther away from the DMA control circuit 4 along line 5 is given higher priority.

That is, if one input/output control device, for example 2-(n-1), receives a DMA request signal from the device on the right side of the figure, it will be directly connected to D.
The DM from the device on the right side of the figure is passed to the MA control circuit 4 side.
It sends out a DMA request signal on line 5 on the condition that there is no A request signal.

When the DMA control circuit detects the DMA request signal (signal *
DAR is logic "0") As will be described later, a DMA enable signal (signal *DA
A emits logic [0-'').

Assuming that the input/output device 2-(n-1) is now sending out a DMA request signal, the device 2-(n-1) detects the above-mentioned DMA permission signal and immediately starts DMA data transfer.
DMA data transfer is performed only during the existence period of the A permission signal.

FIG. 4 shows a DMA processing unit provided in each input/output control device 2 to perform the above operation, and FIG. 5 shows its time chart.

In FIG. 4, numerals 2 and 8 correspond to those in FIG.
is the DMA request signal within the input/output control device, φ1
GRANT is the DMA data transfer enable (i.e. start instruction) signal, *BCO is the downstream line 5
DMA sent on; request signal and the signal *BC
*BE indicates that the DMA request signal is present on line 5 when O is a logic '0'; When the enable signal *BE is logic "0", the common bus 3
is occupied, *BCI is upstream line 5
*DAA is a DMA grant signal sent on line 6-1-, indicating that a DMA request signal is present when the signal BCI is a logic "0"; *Indicating the presence of a DMA grant signal on line 6 when DAA is a logic 'O', 9
is a DMA standby flip. 10 is a matching resistor, 11 to 13 are NAND circuits, 14 is a NOR circuit, and 15 and 16 are NOT circuits.

When there is no DMA request from any human output controller, the signals DMA and GRANT shown in FIG. 4 are both at logic "0", and the signal *BCO. *BE, *BCI
, *DAA are both at logic "1".

As shown in FIG. 5, it is assumed that the ICPU cycle is divided into a DMA data transfer period (DMA) and a central processing unit data transfer period (CPU) by the microprocessor 1 (details will be described later). .

The operation will be explained with reference to FIGS. 4 and 5.

Assume that among the input/output control devices #1, #2, and #3, the input/output control device #3, which has the lowest priority, first issues a DMA request as shown in FIG. 5, as shown in FIG.

(1) In this state, the DMA processing unit 8-3 receives the signal DMA of logic "1".

Since the signal *BCI is at logic "1" at this time, the signal *BCO is set to logic "0" via the NAND circuit 12.

That is, the signal *BCO set to logic "O" is transmitted to the DMA control circuit 4 via the line 5.

(2) On the other hand, since the signal *BCI is logic "1", the NAND circuit 11 outputs logic "0", and the clock φ1
system due to the rise of . Flip in synchronization with clock φ1. A logic "O" is set in the float 9, and the signal Q becomes a logic "0".

(3) On the other hand, the DMA control circuit 4 changes the signal *BCO to logic "0" due to the above operation (1), that is, the signal *DAR shown in FIG.
It is detected that the value becomes logic “0”, and the DMA transfer period (
A signal *DAA of logic "O" is sent out on line 6 in synchronization with DMA).

(4) This causes the NOR circuit 14 shown in FIG.
1" output.

That is, the signal GRANT is set to logic "1" and the signal *BE is set to logic "0".

As a result, the input/output control device 8-3 then occupies the common bus 3 via a circuit section (not shown) and performs DMA data transfer.

Next, suppose that the human output control device #2 issues a DMA request as shown in FIG. 5 b.

(5) In this state, the signal *BCI is at logic "1" in the DMA processing unit 8-2.

Therefore, the DMA data transfer by the input/output control device 2-2 is performed in exactly the same manner as the operations (1) to (4) above.

(6) At this time, when the DMA processing unit 8-2 sets the signal *BCO to logic "0", the signal *BCI becomes logic "0" in the DMA processing unit 8-3 on the downstream side, and the NAND circuit 12 The signal *BCO is set to logic “0” via
” (or if it is already at logic “0”, keep it at logic “0”).

That is, the DMA request issued by the input/output control device on the upstream side is transferred to the downstream side.

Next, assume that the input/output control device #1 issues a DMA request as shown in FIG. 5C.

(7) The operation in this state is exactly the same as the above operations (5) and (6).

At this time, it is assumed that at almost the same time, the human output control device #2 also issues a DMA request, as shown in FIG. 5, d.

(8) In this case, the flip-flop 9 is set in synchronization with the clock φ1 in the DMA processing unit 8-2, but since the signal *BCI is already at logic "0", the NAND circuit 11 is set at logic "1". is output, and logic "1" is set for flip-flop 9.

Therefore, as described above, the DMA control circuit 4 outputs the signal *DAA.
Even if the logic ``0'' is set, the NOR circuit 14 continues to output the logic ``0'', and the signal GRAN is output in the human output control device 8-2.
T never becomes logic "1".

(9) The input/output control device 8-2 sets the signal DMA to logic “1”
D is maintained by the input/output control device 8-1.
When the MA data transfer is completed, the DMA processing unit 8-1 in the input/output control device 2-1 sets the signal *BCO to logic "
1'', at the next rising edge of the clock φ1, the DMA processing unit 8-2 in the human output control device 2-2 generates a flip. Flop 9 is set to logic "0".

That is, DMA transfer is performed by the input/output control device 2-2.

The DMA requests shown in e and f of FIG. 5 below are exactly the same as above, and needless to say, DMA data transfer is performed by the input/output control device 2-1.

In the explanation, it is assumed that the ICPU cycle period is divided into a DMA data transfer period and a central processing unit data transfer period.

That is, as explained with reference to FIG. 2, the main memory access time is shortened and approximately half of the ICPU cycle is sufficient, and if the first half of the ICPU cycle is allocated to the DMA data transfer period. did.

However, depending on the type of main memory, access to the main memory may not always be possible. Thai may be insufficient for only the second half of the above ICPU cycle.

In such a case, processing should be performed to substantially extend the ICPU cycle so that the DMA data transfer and the data transfer by the central processing unit are included in the ICPU cycle.

As described above, according to the present invention, even if the DMA request signal transfer line 5 is wired to all the input/output control devices, only one line 5 is required, and there is no difficulty in wiring.

It also takes a DMA data transfer period divided within the ICPU cycle period, and issues a DMA permission signal in synchronization with the period. DMA immediately in synchronization with the clock
Since data is transferred, the effective utilization rate of the common bus is high.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram for explaining the problems of the conventional method, FIG. 2 is an explanatory diagram for explaining the mode of accessing the main memory, FIG. 3 is a configuration of an embodiment of the present invention, and FIG. An example configuration of a DMA processing unit provided in an input/output control device,
FIG. 5 shows a time chart explaining the operation of the DMA processing unit shown in FIG. In the figure, 1 is a microprocessor, 2-1 to 2-n are input/output control devices, 3 is a common bus, 4 is a DMA control circuit, 5 is a DMA request signal transfer line, 6 is a DMA permission signal line, and 7 is a DMA permission signal line. Clock generation sources 8-1 through 8-n each represent a DMA processing unit.

Claims (1)

[Scope of Claims] 1. A device comprising a plurality of input/output control devices, a main storage device, and a central processing unit connected on a common bus, wherein each of the plurality of input/output control devices and the central processing unit are connected to the common bus. In a data processing system that transfers data by occupying a bus, direct. memory. The direct memory is provided with an access control circuit. Direct memory is connected between the access control circuit and the plurality of input/output control devices. An access request signal transfer line is connected, and a direct memory access permission signal line is connected in a branch connection manner, and the direct memory access control circuit is transferred via the direct memory access request signal transfer line. Direct came. memory. When the access request signal is detected, the direct memory access permission signal is sent to the direct. memory. The input/output control device is configured to issue an access permission signal to the access permission signal line, and each of the input/output control devices is configured so that another input/output control device located upstream of itself is connected to the direct access permission signal line.
memory. Does not issue an access request signal and is connected to the above direct memory. A direct memory that receives the direct memory access permission signal on the condition that it has issued an access request signal. has an access processing unit, and occupies the common bus during the existence period of the direct memory access permission signal to access the direct memory. A direct memory access control method characterized by performing data transfer in response to access requests. 2 Each of the above input/output control devices is connected to the above direct memory. 2. The direct memory access control system according to claim 1, wherein upon receiving an access permission signal, the system determines that the common bus is occupied for the direct memory access control system. 3. Each input/output control device receives direct access from other input/output control devices via the direct memory access request signal transfer line. memory. system on the condition that no access request signal has been transferred. Directly synchronized with the clock. 3. The direct memory access control system according to claim 1, wherein the direct memory access control system is configured to be set in a flip-flop for memory access standby. 4 Direct memory above. The access control circuit performs direct memory access during the ICPU cycle period when the direct memory access request signal from each of the input/output control circuits is present. The above is divided so that a direct memory access data transfer period corresponding to an access request and a central processing unit data transfer period in which the central processing unit occupies the common bus and transfers data exist in a time-sharing manner. Within the direct memory access data transfer period, the above direct. Direct access according to any one of claims 1 to 3, characterized in that it is configured to issue an access permission signal. memory. Access control method.