JPS6172350A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS6172350A
JPS6172350A JP19312384A JP19312384A JPS6172350A JP S6172350 A JPS6172350 A JP S6172350A JP 19312384 A JP19312384 A JP 19312384A JP 19312384 A JP19312384 A JP 19312384A JP S6172350 A JPS6172350 A JP S6172350A
Authority
JP
Japan
Prior art keywords
memory
counter
access
transfer
part 22b
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19312384A
Inventor
Shigeru Hashimoto
Naoyuki Nishimura
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19312384A priority Critical patent/JPS6172350A/en
Publication of JPS6172350A publication Critical patent/JPS6172350A/en
Application status is Pending legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

PURPOSE:To transfer the block data at a high speed by producing plural reading addresses through a memory in response to a reading start address when a mode signal indicates the transfer of block and then outputting the plural corresponding data from a memory element. CONSTITUTION:A memory access control part 22b detects a request for transfer of blocks by a DMA mode signal and switches the lower two bits of a receiver 23 to the side of an address counter 25. A memory element 20 receives the start address of an A-BUS and the addresses of the lower two bits from an address counter 25 via the receiver 23 and performs access. At the same time, a memory control part 22 produces an answer signal SRVO through the part 22b and delivers it to an answer signal line C1. Then a memory 2 counts up a counter 22a which counts the output frequencies of the answer signal to 21 strobes and the counter 25 to give an access to the next word of the memory element 20. Then the part 22b stops the access of the element 20 when the count value of the counter 22a reaches '4' to deliver data four times, i.e., to transmit answer signals four times.
JP19312384A 1984-09-14 1984-09-14 Data transfer control system Pending JPS6172350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19312384A JPS6172350A (en) 1984-09-14 1984-09-14 Data transfer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19312384A JPS6172350A (en) 1984-09-14 1984-09-14 Data transfer control system

Publications (1)

Publication Number Publication Date
JPS6172350A true JPS6172350A (en) 1986-04-14

Family

ID=16302640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19312384A Pending JPS6172350A (en) 1984-09-14 1984-09-14 Data transfer control system

Country Status (1)

Country Link
JP (1) JPS6172350A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182184B1 (en) 1990-04-18 2001-01-30 Rambus Inc. Method of operating a memory device having a variable data input length
US6684285B2 (en) 1990-04-18 2004-01-27 Rambus Inc. Synchronous integrated circuit device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58105363A (en) * 1981-12-17 1983-06-23 Fujitsu Ltd Storage device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58105363A (en) * 1981-12-17 1983-06-23 Fujitsu Ltd Storage device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182184B1 (en) 1990-04-18 2001-01-30 Rambus Inc. Method of operating a memory device having a variable data input length
US6260097B1 (en) 1990-04-18 2001-07-10 Rambus Method and apparatus for controlling a synchronous memory device
US6266285B1 (en) 1990-04-18 2001-07-24 Rambus Inc. Method of operating a memory device having write latency
US6314051B1 (en) 1990-04-18 2001-11-06 Rambus Inc. Memory device having write latency
US6378020B2 (en) 1990-04-18 2002-04-23 Rambus Inc. System having double data transfer rate and intergrated circuit therefor
US6415339B1 (en) 1990-04-18 2002-07-02 Rambus Inc. Memory device having a plurality of programmable internal registers and a delay time register
US6684285B2 (en) 1990-04-18 2004-01-27 Rambus Inc. Synchronous integrated circuit device

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