JPS59223871A - Data transfer system - Google Patents

Abstract

PURPOSE:To simplify the constitution of a system which transfers data between memories by switching buses by using a bus request signal. CONSTITUTION:A shared memory 4 written by a submicroprocessor 5 is transferred to a memory 3 of a main microprocessor 1. In this case, an interruption signal INT is sent to the processor 1 from the processor 5 via an I/O control circuit 8. Then a bus request signal is delivered to a control line 12. The processor 5 receives the request signal and stops the step of an executed program to deliver a bus confirmation signal. Bus switching circuits 2 and 2' are actuated by the bus request signal to switch the memory 4 to the bus side of the processor 1. Thus the memory 4 is put under the control of the processor 1. When the processor 1 detects a bus request reception signal, the data on the address designated by the memory 4 is transferred to the address designated by the memory 3 of the processor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for transferring data between memories by switching buses.

In recent years, devices using microprocessors have come into widespread use. When using the currently available 8-bit microprocessors as devices that perform various types of processing while communicating at high speeds, the processing speed cannot be said to be fast enough. My mileage? High-speed systems are supported by either using all the processors or using multiple 8-bit microprocessors to distribute processing functions.

In this way, when a plurality of microprocessors perform processing operations, it is necessary to transfer the memory data of each microprocessor to each other in order to allow each microprocessor to perform its operations organically.

As a conventional data transfer method for this purpose, a DMA (direct memory access) method is used. D.M.A.
In the case of this method, in order to directly transfer data between memories without going through a microprocessor, the address signal generation circuit of the transfer memory, the start address, and address length (transfer data length) of the above address signal generation circuit are controlled. The drawback is that it requires a circuit and is complicated and expensive.

An object of the present invention is to provide a data transfer method with a simple configuration.

The data transfer method of the present invention includes a first microprocessor, a second microprocessor, means for sending an interrupt signal from the first microprocessor to the second microprocessor, a shared memory, and a second microprocessor. means for transmitting a bus request signal from the second microprocessor to the first microprocessor; means for transmitting a path request acceptance signal from the first microprocessor to the second microprocessor; a control line for controlling the data bus, address bus, and writing/reading of the shared memory in accordance with the bus request signal; means for switching connection from the microprocessor side to the second microprocessor; and means for transferring the contents of the shared memory to the memory of the second microprocessor according to an inter-memory transfer command from the second microprocessor. It is characterized by having the following.

Next, embodiments of the present invention will be described in detail using the drawings.

FIG. 1 shows an embodiment of the present invention. That is, for example, when the contents of the shared memory 4 written by the sub-microprocessor 5 are transferred to the memory 3 of the main microprocessor, the data is in a state where it can be transferred from the shared memory 4 to the memory 3 of the main microprocessor. When the sub-
From the microprocessor 5 to the main Φ microprocessor via the I10 control circuit 8 of the sub microprocessor. Sends an interrupt signal (INT) to l. In the interrupt routine of the program of the main microprocessor 1, a bus request (BUSREQ) signal is output to the control line 12 to the sub-microprocessor 5. This signal is input to the sub-processor via the I10 control circuit 9 of the main microprocessor.
The microprocessor 5 stops at the step of the executed program and outputs a bus confirmation (BUSAK) signal.

The bus switching circuit 2.2' operates according to the bus request signal,
The shared memory 4 is switched to the bus side of the main microprocessor l and placed together with the memory 3 under the control of the main microprocessor l. Here, when the main microprocessor 1 detects the I-X request acceptance signal, it transfers the data at the specified address in the shared memory 4 to the specified address in the memory 3 of the main microprocessor using an inter-memory transfer command.

When the transfer of the required memory area is completed, the main microprocessor l stops outputting the bus request number. As a result, the shared memory 1 is again placed under the control of the sub-microprocessor 5, and normal processing operations are resumed.

6.7 are the main microprocessor and sub microprocessor, respectively.
These are microprocessors R and OM.

In the above example, we have described the format of the main microprocessor and sub microprocessor, but by configuring the same circuit configuration as above for two or more microprocessors, a data transfer method that does not have a master-slave relationship can also be realized. I can do it.

As described above, according to the present invention, a data transfer system with a simple configuration can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. l... Main microprocessor, 2.2'
°“・・・Bus switching circuit% 3・・・・・・Main・
Microprocessor memory, 4...Shared memory, 5...Sub microprocessor, 6...
... Main microprocessor ROM, 7...
...Sub microprocessor ROM, 8...
...I10 control circuit of sub-microprocessor, 9
...■10 control circuit of main microprocessor, 10...address bus. 11...Data bus, 12...Control line.

Claims (1)

[Claims] a first microprocessor and a second microprocessor; means for sending an interrupt signal from the first microprocessor to the second microprocessor; a shared memory; means for transmitting a bus request signal to the first microprocessor; means for transmitting a bus request acceptance signal from the first microprocessor to the second microprocessor; and means for transmitting the bus request signal to the second microprocessor. means for reading an acceptance signal from a data bus; and a control line for controlling the data bus, address bus, and writing/reading of the shared memory in accordance with the bus request signal, all from the first microprocessor side to the second microprocessor side. and means for transferring all data stored in the shared memory to the memory of the second microprocessor in accordance with an inter-memory transfer command from the second microprocessor. Data transfer method.