JPS6285360A - Serial data input/output circuit - Google Patents

Abstract

PURPOSE:To vary freely clock speed by starting a clock generating circuit as the execution of a prescribed instruction on a program and generating a clock pulse. CONSTITUTION:A CPU 101 executes an instruction in accordance with the program of a ROM 102, and when the execution of the program is migrated to execution of an instruction for setting the clock of a serial transfer to '1' or '0', a control signal is sent to a clock generating circuit 104 so that a clock signal CK becomes '1' or '0', and a clock pulse is generated. Also, the CPU 101 sends a data to be transferred to a shift register 105 through a data setting circuit 106 in accordance with a program instruction in the same way, and sends it out as a data signal DA synchronizing with the clock signal. In this case, the generation of the clock signal on the program stored in the ROM 102 changes only a data related to a control of the circuit 104, and the period of the signal CK can be varied freely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial data input/output circuit used, for example, in a one-chip microcomputer or the like to transfer data to an element of another computer or the like.

[Conventional technology]

Data transfer methods include a serial transfer method that transfers data serially in synchronization with a clock, and a parallel transfer method that transfers data in parallel. Of these, the serial transfer method is used for transfer between microcomputers, etc. is commonly used.

Conventionally, this type of transfer has been performed using a circuit configuration as shown in FIG. 4, for example. That is, the 8-bit data set circuit 1 sets the data to be sent in the 8-bit shift register 2. On the other hand, clock signal generation circuit 3
The clock signal CK is input to the 8-bit shift register 2, and at the same time, the data signal DA and the clock signal CK are output to the outside. By using such a configuration, data can be serially transferred in synchronization with the clock by generating a clock signal after setting the data.

[Problem that the invention seeks to solve]

As described above, since the generation of the clock signal in the conventional serial transfer method is performed purely by a hardware configuration, there are limitations for each stock. For example, when the line connecting the sending and receiving microcomputers is long, the clock speed needs to be slowed down. Furthermore, it is necessary to select a microcomputer on the transmitting side that has a clock signal speed that matches the receiving speed of the microcomputer on the receiving side of data and clock signals.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a serial data input/output circuit that can arbitrarily change the clock speed.

[Means for solving problems]

In this invention, a clock generation circuit is activated as a predetermined instruction on a program is executed by a processor unit such as a microprocessor, and a clock pulse is generated.

[For production]

If the program is changed to change the execution cycle of the above instructions, the clock speed will change.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Second
As shown in the figure, consider the case where data from an l-chip microcomputer 11 is transferred to another microcomputer 12. Data signal DA is sent in synchronization with clock signal CK.

In summary, as shown in Figure 3, one bit (11'' or %ol) of the data signal DA is sent for one pulse of the clock signal CK. It is possible to send 8 pieces of data.

In order to obtain this data signal DA and clock signal CK,
The micro combinator 11 has a configuration as shown in FIG. Of course, only the elements necessary for explaining the invention are illustrated.

In FIG. 1, 101 is a processor unit (CPU
), 102 is a fixed memory (ROM) that stores programs and fixed data, 103 is a variable memory (RAM) that stores variable data, 104 is a clock generation circuit connected to the CPU 101 via an output port, 105
is an 8-bit shift register similar to that described above. 1
06 is also an 8-bit data set circuit and is connected to cPUlol via an input/output port.

The CPU 101 loads the program data previously stored in the ROM 102, and when the program moves to the row according to the program, the CPU 101 changes the clock signal CK to %IJ.
or 10', a control signal is sent to the clock generation circuit 104 to generate a clock pulse. Also, C
Similarly, PUIQI inputs data to be transferred to the data set circuit 106 in accordance with instructions on the program. The input data is transferred to the shift register 105 and sent out as a data signal DA synchronized with the clock signal.

The CPU 101 executes various arithmetic instructions and the like for the above processing and other processing according to the above programs, and for this purpose, various data are exchanged with the RAM 103.

Here, the period of the clock signal can be freely changed by simply changing the data regarding the generation of the clock signal and the control of the clock generation circuit 104 on the program stored in the ROM 102.

Therefore, data can be transferred from the microcombiator 11 no matter what reception speed the microcomputer 12 on the receiving side has.

Although the case of transmission has been explained above, the case of reception is also the same, and according to the data input/output circuit of the present invention, no matter what lock speed the data signal is sent from the transmitting side, it can be processed in advance according to the program. By setting the data according to the seven patterns, it can be received correctly.

〔Effect of the invention〕

As described above, according to the present invention, the clock signal for serial data input/output is generated by software as the execution of a predetermined command on the program, so it can be easily adapted to any system. This has the effect of freeing you from hardware constraints.

[Brief explanation of drawings]

1 to 3 are diagrams showing one embodiment of the present invention, and FIG. 1 is a block diagram showing the configuration of a microcomputer;
Figure 2 is a block diagram showing connections between microcomputers that perform data transfer, Figure 3 is a timing chart showing the relationship between serially transferred data signals and clock signals, and Figure 4 is a block diagram showing a conventional example. be. 11.12...Φ・Microcomputer, 101-・
... Processor unit (CPU), 102 ... Fixed memory (ROM) that stores the program, 104@.
φ/clock generation circuit, 105...shift register, 106...φ data set circuit.

Claims (1)

[Claims] A serial data input/output circuit that inputs and outputs data in synchronization with a clock signal sent from a clock generation circuit using a shift register, and includes a processor unit that executes instructions according to a prestored program,
A serial data input/output circuit characterized in that a clock generation circuit is activated to generate clock pulses as a predetermined instruction on a program is executed.