JPH07230304A - Dual control method for pc system - Google Patents
Dual control method for pc systemInfo
- Publication number
- JPH07230304A JPH07230304A JP6044799A JP4479994A JPH07230304A JP H07230304 A JPH07230304 A JP H07230304A JP 6044799 A JP6044799 A JP 6044799A JP 4479994 A JP4479994 A JP 4479994A JP H07230304 A JPH07230304 A JP H07230304A
- Authority
- JP
- Japan
- Prior art keywords
- synchronization
- signals
- pcs
- signal
- interruption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、二台のプログラマブル
コントローラ(以下、PCと略す)を用いたPCシステ
ムにおけるデュアル制御方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual control method in a PC system using two programmable controllers (hereinafter abbreviated as PC).
【0002】[0002]
【従来の技術】PCのデュアルシステムは、同一のプロ
グラムを二台のPCに格納し二台のPCを並列に運転す
ることにより、片方のPCに故障が発生した場合でもも
う一方のPCで運転を継続することによりシステムの信
頼性を高めるPCシステムである。デュアルシステムの
並列運転においては、一台のPCの故障時に継続運転を
確実に保証するためには、常に二台のPCの内部状態を
一致させておく必要がある。このため、従来技術では、
並列運転開始時に二台のPC間の内部状態を一致さると
ともに、並列運転実行時には同一の入力データを二台の
PCに同時に取り込みプログラムを実行させる方法が一
般に採用されていた。2. Description of the Related Art A dual system of PCs operates by storing the same program in two PCs and operating the two PCs in parallel, so that even if one PC fails, the other PC runs. It is a PC system that enhances system reliability by continuing. In the parallel operation of the dual system, it is necessary to always match the internal states of the two PCs in order to ensure the continuous operation when one PC fails. Therefore, in the conventional technology,
In general, a method is adopted in which the internal states of two PCs are matched at the start of parallel operation, and the same input data is simultaneously taken into two PCs to execute a program when parallel operation is executed.
【0003】[0003]
【発明が解決しようとする課題】ところが、従来技術で
は、割り込み信号により複数のタスクを切り替えて前記
各タスクのプログラムを実行するPCにおいては、二台
のPC間のCPUクロックの微妙な差異による割り込み
受付タイミングの不一致によりタスク切り替えの同期性
が確保できないため、二台のPCの内部状態の一致性を
常に確保することができなかった。そこで本発明は、こ
のような問題を解決し、割り込み信号により複数のタス
クを切り替えて前記各タスクのプログラムを実行するP
Cにおいても、内部状態の一致性を常に確保することを
目的とする。However, according to the prior art, in a PC that switches a plurality of tasks by an interrupt signal to execute the program of each task, an interrupt due to a subtle difference in CPU clocks between two PCs. Since the task switching synchronism cannot be ensured due to the mismatch of the reception timings, the consistency of the internal states of the two PCs cannot always be ensured. Therefore, the present invention solves such a problem and switches a plurality of tasks by an interrupt signal to execute the program of each task.
Even in C, the purpose is to always ensure the consistency of the internal state.
【0004】[0004]
【課題を解決するための手段】上記課題を解決するた
め、本発明では、割り込み信号により複数のタスクを切
り替えて前記各タスクのプログラムを実行するPCのデ
ュアルシステムにおいて、前記プログラム実行時に前記
各PCからプログラムに従って同期指令信号を出し、前
記全PCからの同期指令が出されたことを確認して前記
各PCに同期完了信号を返し、前記各PCへの共通割り
込み信号が存在している場合には、前記同期完了信号と
同期して前記各PCに割り込み信号を発生させるもので
ある。In order to solve the above problems, according to the present invention, in a dual system of a PC that switches a plurality of tasks by an interrupt signal to execute a program of each task, each PC is executed when the program is executed. In accordance with the program, confirms that all the PCs have issued the synchronization command, returns a synchronization completion signal to each of the PCs, and a common interrupt signal to each of the PCs is present. Is to generate an interrupt signal in each of the PCs in synchronization with the synchronization completion signal.
【0005】[0005]
【作用】上記手段によれば、二台のPCからの同期指令
信号に対して同期が取られるとともにその同期完了信号
と同期して二台のPCに対して同じ割り込みが発生でき
るので、割り込み信号によるタスク切り替えの同期性が
保証される。これにより、二台のPC間の内部状態の一
致性が常に確保される。According to the above means, the same interrupt can be generated for the two PCs in synchronization with the synchronization command signal from the two PCs and in synchronization with the synchronization completion signal. The synchronization of task switching by is guaranteed. As a result, the consistency of the internal state between the two PCs is always ensured.
【0006】[0006]
【実施例】以下、本発明の実施例を図に基づいて説明す
る。図1は本発明によるデュアルシステムの構成例で
1、2はデュアルシステムを構成する二台のPCを示し
ており、3、4は各PCに格納されているプログラムを
実行するCPUを示している。二台のPCの各CPU
は、プログラムを実行するとともに、プログラムに指定
されたタイミングで同期制御装置5に対して同期指令
6、7を出力する。同期制御装置5は、二台のPCから
の同期指令信号6、7を受信し、二台のPCからの同期
指令信号6、7が揃ったことを確認して同期完了信号
8、9を返すとともに、共通割り込み信号12が存在し
ていれば、同期完了信号と同期して二台のPCに対して
同じ割り込み信号10、11を発生させる。図2はデュ
アルシステムの同期制御動作タイミングチャートであ
る。二台のPCは図2の6、7に示すようにプログラム
で決められた間隔で同期実行指令を出力し、同期完了信
号を待つ。同期制御装置5は、図2の8、9に示すよう
に二台のPCからの同期指令6、7が両方とも出力され
た時点で各PCに対して同期完了信号8、9を返す。こ
の時、図2の共通割り込み信号12が存在していれば、
図2の10、11に示すように同期完了信号8、9に同
期して二台のPCに対して割り込み信号10、11を発
生させる。このように、二台のPCへの割り込み信号は
同期完了信号8、9に同期して発生するため、割り込み
によるタスク切り替えの同期性が保証され、二台のPC
の内部状態の一致性が常に確保される。なお、同期指令
信号と同期完了信号の具体的な実施例を挙げると、各C
PUの同期指令信号はメモリまたは入力ポートからの読
み出し命令により実現でき、同期完了信号は前記読み出
し命令に対する読み出し完了信号により実現できる。一
般的なCPUでは、通常、前記読み出し命令は基本命令
として準備されており高速に実行可能であり、前記読み
出し命令に応答する簡単な同期制御装置で高速な同期動
作を実現でき、オーバヘッドの小さいデュアルシステム
を実現することが可能である。また、同期指令信号の間
隔は、割り込み応答速度を考慮して任意に決定すること
が可能である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration example of a dual system according to the present invention. Reference numerals 1 and 2 denote two PCs constituting the dual system, and 3 and 4 denote CPUs that execute programs stored in the respective PCs. . Each CPU of two PCs
Executes the program and outputs synchronization commands 6 and 7 to the synchronization control device 5 at the timing specified by the program. The synchronization control device 5 receives the synchronization command signals 6 and 7 from the two PCs, confirms that the synchronization command signals 6 and 7 from the two PCs are complete, and returns the synchronization completion signals 8 and 9. At the same time, if the common interrupt signal 12 is present, the same interrupt signals 10 and 11 are generated for the two PCs in synchronization with the synchronization completion signal. FIG. 2 is a timing chart of synchronous control operation of the dual system. As shown by 6 and 7 in FIG. 2, the two PCs output synchronization execution commands at intervals determined by the program and wait for a synchronization completion signal. As shown by 8 and 9 in FIG. 2, the synchronization control device 5 returns the synchronization completion signals 8 and 9 to each PC when both the synchronization commands 6 and 7 from the two PCs are output. At this time, if the common interrupt signal 12 of FIG. 2 exists,
As shown by 10 and 11 in FIG. 2, the interrupt signals 10 and 11 are generated for the two PCs in synchronization with the synchronization completion signals 8 and 9. In this way, since the interrupt signal to the two PCs is generated in synchronization with the synchronization completion signals 8 and 9, the synchronism of task switching by the interrupt is guaranteed, and the two PCs
The consistency of the internal state of is always ensured. It should be noted that each of the C
The PU synchronization command signal can be realized by a read command from the memory or the input port, and the synchronization completion signal can be realized by a read completion signal corresponding to the read command. In a general CPU, the read command is usually prepared as a basic command and can be executed at a high speed, and a simple synchronous control device that responds to the read command can realize a high-speed synchronous operation and a dual overhead having a small overhead. It is possible to realize the system. Further, the interval of the synchronization command signal can be arbitrarily determined in consideration of the interrupt response speed.
【0007】[0007]
【発明の効果】以上述べたように、本発明によれば、割
り込み信号により複数のタスクを切り替えて各タスクの
プログラムを実行するPCのデュアルシステムにおい
て、簡単な同期制御装置により、割り込み信号による各
PCのタスク切り替えの同期性を保証する高速な同期制
御が可能なPCのデュアルシステムを実現することが可
能である。As described above, according to the present invention, in a dual system of a PC which switches a plurality of tasks by an interrupt signal and executes a program of each task, a simple synchronous control device is used to control each interrupt signal. It is possible to realize a dual PC system capable of high-speed synchronization control that guarantees the synchronization of task switching of the PC.
【図1】デュアルシステムの構成例[Fig. 1] Configuration example of dual system
【図2】デュアルシステムの同期制御動作タイミングチ
ャートFIG. 2 is a timing chart of synchronous control operation of a dual system.
【符号の説明】 1、2 デュアルシステムを構成する二台のPC 3、4 PCのプログラムを実行するCPU 5 同期制御装置 6 No.1PCの同期指令信号 7 No.2PCの同期指令信号 8、9 各PCへの同期完了信号 10 No.1PCへの割り込み信号 11 No.2PCへの割り込み信号 12 共通割り込み信号[Explanation of Codes] 1, 2 Two PCs constituting a dual system 3, CPU for executing programs of 4 PC 5 Synchronous control device 6 No. 1 PC synchronous command signal 7 No. 2 PC synchronous command signal 8, 9 Synchronization completion signal to each PC 10 Interrupt signal to No.1 PC 11 Interrupt signal to No.2 PC 12 Common interrupt signal
Claims (1)
替えて前記各タスクのプログラムを実行するPCのデュ
アルシステムにおいて、前記プログラム実行時に前記各
PCからプログラムに従って同期指令信号を出し、前記
全PCからの同期指令が出されたことを確認して前記各
PCに同期完了信号を返し、前記各PCへの共通割り込
み信号が存在している場合には、前記同期完了信号と同
期して前記各PCに割り込み信号を発生させることを特
徴とするPCシステムのデュアル制御方法。1. In a dual system of a PC that switches a plurality of tasks by an interrupt signal to execute a program of each task, a synchronization command signal is issued from each PC according to the program when the program is executed, and synchronization from all the PCs is performed. After confirming that a command has been issued, a synchronization completion signal is returned to each of the PCs, and if a common interrupt signal to each of the PCs is present, the PCs are interrupted in synchronization with the synchronization completion signal. A dual control method for a PC system, characterized in that a signal is generated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6044799A JPH07230304A (en) | 1994-02-18 | 1994-02-18 | Dual control method for pc system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6044799A JPH07230304A (en) | 1994-02-18 | 1994-02-18 | Dual control method for pc system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07230304A true JPH07230304A (en) | 1995-08-29 |
Family
ID=12701479
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6044799A Pending JPH07230304A (en) | 1994-02-18 | 1994-02-18 | Dual control method for pc system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07230304A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002109295A (en) * | 2000-09-28 | 2002-04-12 | Visual Japan Inc | Pos system, pos server, store terminal, sales managing method and recording medium |
JP2008135027A (en) * | 1996-12-13 | 2008-06-12 | Emerson Process Management Power & Water Solutions Inc | Drop in fully redundant, workstation-based distributed process control system |
-
1994
- 1994-02-18 JP JP6044799A patent/JPH07230304A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008135027A (en) * | 1996-12-13 | 2008-06-12 | Emerson Process Management Power & Water Solutions Inc | Drop in fully redundant, workstation-based distributed process control system |
JP2002109295A (en) * | 2000-09-28 | 2002-04-12 | Visual Japan Inc | Pos system, pos server, store terminal, sales managing method and recording medium |
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