JPS60144829A - Microprogram control system - Google Patents

Microprogram control system

Info

Publication number
JPS60144829A
JPS60144829A JP42184A JP42184A JPS60144829A JP S60144829 A JPS60144829 A JP S60144829A JP 42184 A JP42184 A JP 42184A JP 42184 A JP42184 A JP 42184A JP S60144829 A JPS60144829 A JP S60144829A
Authority
JP
Japan
Prior art keywords
microprogram
microprogram control
memory
arithmetic device
controlling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP42184A
Other languages
Japanese (ja)
Inventor
Yukio Ito
伊藤 行雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP42184A priority Critical patent/JPS60144829A/en
Publication of JPS60144829A publication Critical patent/JPS60144829A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the size of an arithmetic device which is controlled by one microprogram and shorten a processing time by parallel of processing by performing one operation partially by plural microprograms. CONSTITUTION:The sart of an operation is indicated to microprogram controllers 1 and 6 at the same time. The microprogram controller 1 while controlling a program sequence by itself indicates an arithmetic device 3 to read data out of a register group and store it memory. The microprogram controller 6 while controlling the program sequence by itself indicates an arithmetic device 8 to read memory for old time control information on a task and a timer and generate and store new time control information on the task in the memory. Consequently, the operation is carried out by performing said processes in parallel.

Description

【発明の詳細な説明】 〔発明の輯する技術分野〕 本発明は、複数のマイクロプログラム制御装置を有する
マイクロプログラム制御システムに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a microprogram control system having a plurality of microprogram control devices.

〔従来技術〕[Prior art]

最近の情報処理装置分野においては、その性能向上の請
求に伴い演算装置が大型化してきており、これを1つの
マイクロプログラムによシ制御することは、その物理的
位置関係において、制御信号用配線長を長くすることに
なり、これに伴い制御信号の伝搬時間が延びるために、
マシンサイクル時間が大きくなってしまっている1 また、情報処理装置分野においては機能の向上要求も大
きく、1つのオペレーションの中で実行されるべき動作
が複雑化してきておシ、これを1つのマイクロプログラ
ムで処理することは、条件分岐等のためにマイクロ−プ
ログラムの処理ステップ数が増加し、性能低下を招くこ
ととなっている。
In recent years in the field of information processing equipment, arithmetic units have become larger due to demands for improved performance, and controlling them with a single microprogram is difficult due to the physical location of the control signal wiring. This will increase the control signal propagation time, so
Machine cycle time has become long.1 Furthermore, in the field of information processing equipment, there is a great demand for improved functionality, and the operations that must be executed in one operation are becoming more complex. Processing using a program increases the number of processing steps of the microprogram due to conditional branching, etc., resulting in a decrease in performance.

〔発明の目的〕[Purpose of the invention]

本発明の目的は1.1つのオペレーションを複数のマイ
クロプログラムで分割して実行することによシ、1つの
マイクロフログラムで制御する演算装置を小さくシ、そ
の物理的な距離を小さくするとともに、処理の並行実行
によって処理時間の短縮を図るようにしたマイクロプロ
グラム制御システムを提供することにある。
The purpose of the present invention is 1. By dividing and executing one operation by multiple microprograms, the arithmetic unit controlled by one microprogram can be made smaller, the physical distance between them can be shortened, and the processing An object of the present invention is to provide a microprogram control system in which processing time is shortened by parallel execution of .

〔発明の塾成〕[School of invention]

本発明によるマイクロプログラム制御システムは、各マ
イクロ命令シーケンスを各々独立に制御し得る複数のマ
イクロプログラム制御装置と、これらに対応して設けら
れかつその対応するマイクロプログラムによシ制御され
る複数の演算装置とを備え、 各演り、装置が同時に動作し得るように各マイクロプロ
グラム制御装置を一斉に起動し、かつ起動された各マイ
クロプログラム制御装置が同期して動作するように制御
する構成・となっている。
A microprogram control system according to the present invention includes a plurality of microprogram control devices capable of independently controlling each microinstruction sequence, and a plurality of operations provided correspondingly to these devices and controlled by the corresponding microprograms. and a configuration for starting each microprogram control device at the same time so that each performance and device can operate simultaneously, and controlling the activated microprogram control devices so that they operate synchronously. It has become.

〔発明の寅施例〕[Example of invention]

以下、本発明罠ついて図面を参照して詳細に説明する。 Hereinafter, the features of the present invention will be explained in detail with reference to the drawings.

図は本発明の一実施例を示すブロック図であシ、本図に
おいて、マイクロプログラム制御装@1は当該装置1内
の制御メモリ(図示せず)から読み出したマイクロ命令
を制御線2を介して演算装置3に送シ、当該装置3の制
御を行なう。演算装置3はレジスタ群4およびメモリ5
と接続され、マイクロプログラム制御装置1によシ指示
された動作を実行する5、マイクロプログラム制#装置
6はマイクロプログラム制御装置1と同様に、制御線7
を介して演舞回路8を制御する。演算回路8はメモリ5
およびタイマ9と接続され、マイクロプログラム制御装
置6によシ指示された動作を実行する。マイクロプログ
ラム制御装置6は信号線10を介してマイクロプログラ
ム制御装置1よシ同期信号、を受け堆シ、マイクロプロ
グラム制御装力1と同期して動作する。
The figure is a block diagram showing one embodiment of the present invention. In this figure, a microprogram control device @1 sends microinstructions read from a control memory (not shown) in the device 1 via a control line 2. The data is then sent to the arithmetic device 3 and the device 3 is controlled. Arithmetic device 3 has register group 4 and memory 5
The microprogram control device 6 is connected to the control line 7 and executes the operation instructed by the microprogram control device 1.
The performance circuit 8 is controlled via the control circuit 8. Arithmetic circuit 8 is memory 5
and timer 9, and executes operations instructed by microprogram control device 6. The microprogram control device 6 receives a synchronization signal from the microprogram control device 1 via a signal line 10, and operates in synchronization with the microprogram control device 1.

ここで、タスク切替時等に発生するレジスタ群のメモリ
への格納とタスク処理時間等を管理するための時間管理
情報の生成とが、1つのオペレーション単位としての実
行を定義された場合を例にとると、このオペレージロン
はマイクロプロf−yムレベルでは下bξ:の6つの動
作に分解して認識できる。すなわち、 α) レジスタ群の読出し く2)読み出したレジスタ群のメモリへの格納(3)当
該タスクの旧時riJI管理情報のメモリからのル゛1
出し く4) タイマの読出し く5)当該タスクの断時間管理情報の生成(6)断時間
管理情報のメモνへの格納従来の情報処理装置において
は、上記オペレーションは(1)〜(6)の順を追って
実行されていた。しかしながら、(1)〜(2)の動作
と(3)〜(6)の動作とは互いに独立に実行できるた
め、本発明にょカば、まず本オペレーシミンの開始をマ
イクロプログラム制御装置1および6に対して同時に指
示すると、マイクロプログラム制御装置1は自分自身で
マイクロプログラムシーケンスを管理しつつ上記(1)
〜0)の動作を願を迫って演算装置3に指示して行く。
Here, let's take as an example a case where the storage of registers in memory that occurs when switching tasks, etc., and the generation of time management information for managing task processing time, etc. are defined to be executed as one operation unit. Then, this operation can be recognized by being broken down into the following six operations at the microprogram level. That is, α) Read the register group 2) Store the read register group in the memory (3) Read the old riJI management information of the task from the memory
Output 4) Read out the timer 5) Generate time-out management information for the task (6) Store time-out management information in memo ν In conventional information processing devices, the above operations are (1) to (6). It was executed in the following order. However, since the operations (1) to (2) and the operations (3) to (6) can be executed independently of each other, the present invention first starts this operation by controlling the microprogram controllers 1 and 6. , the microprogram control device 1 manages the microprogram sequence itself and executes the above (1).
~0) is requested to the arithmetic unit 3.

またマイクロプログラム制御装置6も自分自身でマイク
ロプログラムシーケンスを管理しつつ上記(3)〜(6
)の動作を加を追っそ演算装置8に指示して行く。これ
によシ、上記オペレージロンは(1)〜C)と(3)〜
(6)とが並行して実行されるため、大幅な処理時間の
短縮が実りできる。
In addition, the microprogram control device 6 also manages the microprogram sequence by itself and
) and instructs the arithmetic unit 8 to follow the addition. In addition to this, the above operations are (1) to C) and (3) to
(6) is executed in parallel, resulting in a significant reduction in processing time.

また、マイクロプログラム制御装置1と演算装置8との
間及びマイクロプログラム制御憧装置6と演算装置3と
の間には夫々制御信号が存在しkいので、これらが互い
に物理的に離れていたとしてもマシンサイクル時間を長
ぐすることはない。
Furthermore, since there are control signals between the microprogram control device 1 and the arithmetic device 8 and between the microprogram control device 6 and the arithmetic device 3, it is assumed that they are physically separated from each other. does not increase machine cycle time.

以上欽明したように、本発明によれは、1つのオペレー
ションを複数のマイクロプログラムで分割し、て並行実
行するように構成したので、マシンサイクル時間の短縮
や処理サイクル数の削減が可能となシ、情報処理装置の
性能を大幅に改善できるという優れた効果が得られる。
As explained above, according to the present invention, since one operation is divided into multiple microprograms and executed in parallel, a system that can shorten machine cycle time and reduce the number of processing cycles can be realized. , an excellent effect can be obtained in that the performance of the information processing device can be significantly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例を示すブロック図である。 1.6・・・・・・マイクロプログラム制御装置、3゜
8・・・・・・演算装置。
The figure is a block diagram showing one embodiment of the present invention. 1.6...Microprogram control device, 3゜8...Arithmetic device.

Claims (1)

【特許請求の範囲】[Claims] 各マイクロプログラムを各々独立に制御し得る複数のマ
イクロプログラム制御装置と、前記株数のマイクロプロ
グラム制御装置に各々対応して設けられかつ対応するマ
イクロプログラムによシ制御される複数の演算装置とを
備え、所定のオペレーション単位の実行に際して前記複
数の演舞装置が同時に動作し得るように前記複数のマイ
クロプログラム制御装置を起動し、かつ該オペレーショ
ン単位の実行過程で前記複数のマイクロプログラム制御
装置が同期して動作するように制御することを特徴とす
るマイクロプログラム制御システム。
A plurality of microprogram control devices capable of independently controlling each microprogram, and a plurality of arithmetic units provided corresponding to the number of microprogram control devices and controlled by the corresponding microprograms. , activating the plurality of microprogram control devices so that the plurality of performance devices can operate simultaneously when executing a predetermined unit of operation, and synchronizing the plurality of microprogram control devices in the process of executing the unit of operation. A microprogram control system characterized by controlling operations.
JP42184A 1984-01-05 1984-01-05 Microprogram control system Pending JPS60144829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP42184A JPS60144829A (en) 1984-01-05 1984-01-05 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP42184A JPS60144829A (en) 1984-01-05 1984-01-05 Microprogram control system

Publications (1)

Publication Number Publication Date
JPS60144829A true JPS60144829A (en) 1985-07-31

Family

ID=11473336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP42184A Pending JPS60144829A (en) 1984-01-05 1984-01-05 Microprogram control system

Country Status (1)

Country Link
JP (1) JPS60144829A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293586A (en) * 1988-09-30 1994-03-08 Hitachi, Ltd. Data processing system for development of outline fonts

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49132947A (en) * 1973-04-25 1974-12-20
JPS5390840A (en) * 1977-01-21 1978-08-10 Mitsubishi Electric Corp Arithmetic processor of microprogram control
JPS55143663A (en) * 1979-04-25 1980-11-10 Nec Corp Data processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49132947A (en) * 1973-04-25 1974-12-20
JPS5390840A (en) * 1977-01-21 1978-08-10 Mitsubishi Electric Corp Arithmetic processor of microprogram control
JPS55143663A (en) * 1979-04-25 1980-11-10 Nec Corp Data processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293586A (en) * 1988-09-30 1994-03-08 Hitachi, Ltd. Data processing system for development of outline fonts

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