JPH04347756A - Channel state read system - Google Patents

Abstract

PURPOSE:To process a channel state storage instruction which is to store state information on a channel connected to an input/output processor on a main storage device in a computer system. CONSTITUTION:In the computer system in which plural instruction processors 1 are connected to the input/output processor 3 having plural channels 4 through a system controller 2 and which has the main storage device 5 shared by the respective instruction processors 1 and the input/output processor 3, a private area 20 shared by the systems is provided on the storage device 5 to which the instruction processors 1 and the input/output processor 3 can access, and the input/output processor 3 stores information on the channel state in the private area 20 at every prescribed time. For executing the channel state storage instruction of the instruction processor 1, information on the channel state stored in the private area 20 is read from the input/output processor 3 and it is storage-processed in the designated address of the main storage device 5.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a channel state reading method, and particularly to an instruction processor, an input/output processing device,
In a computer system consisting of a system control device and a main memory device, this relates to a channel state read method that can quickly process a channel state storage instruction that stores state information of a channel connected to an input/output processing device on the main memory device. It is.

0002

[Background Art] In recent computer systems, in order to reduce the burden on the operating system (OS) for input/output processing, input/output requests have been changed from queuing of input/output requests, which was previously performed by the OS, to input/output devices. There is a tendency for output channel selection processing to be performed by hardware. In addition, by monitoring the operating status of channels, channel utilization rates are determined, and system operations are performed to optimally allocate channels and perform more efficient input/output operations. Therefore, in order to obtain the channel utilization rate, the instruction processor executes a channel state storage instruction to capture channel state information.

[0003] Conventionally, the processing of such a charge state storage instruction has been similar to the processing of an input/output instruction in which the instruction is processed in synchronization with an input/output processing device via a system control device, as described below. Processing method is executed.

FIG. 3 is a block diagram showing the configuration of a computer system for explaining the processing of a conventional channel state storage command. This will be explained with reference to FIG. For example, when a channel state storage instruction is executed by the instruction processor (IP) 1, the storage destination address of the channel state information given as an operand of the instruction is first stored in the main memory (as a dedicated area for hardware control). The information is stored in an input/output control block (IOCB) 6 in a dedicated area for input/output processing in a hardware system area (HSA) provided in a part of the storage area of the MS) 5. After storing the storage address of the channel state information in the IOCB 6, the instruction processor 1 sends the address to the system control unit (SC) 2.
A processing request (activation request) signal for the channel state storage command is issued to the input/output processing device 3 via control signal lines 8A and 8B.

[0005] When the input/output processing device 3 receives a startup request, it reads the channel state storage destination address from the above-mentioned IOCB 6, and before and after that, the input/output processing device 3 reads the state of each channel connected to its own input/output processing device 3. Check the status of each channel in 1-bit units, that is, if it is 0, it is inactive, if it is 1, it is in operation, and so on.
Channel state information reflecting the state of each channel bit by bit is stored at the channel state storage destination address on the main storage device designated by the above-mentioned IOCB6. After storing the channel storage information, the input/output processing device 3 issues an instruction processing completion report signal to the instruction processor 1 via the system control device 2 via the signal lines 9A and 9B. The instruction processor 1 receives the instruction processing completion report signal and ends the instruction processing of this channel state storage instruction.

[0006] In this manner, the processing of the channel state storage instruction is executed as a synchronous instruction that executes instruction processing in synchronization between the instruction processor and the input/output processing device. An example of an instruction that involves this type of synchronous processing is an SIO (Start I/O) instruction that performs processing in synchronization with an input/output device and an input/output control device via a channel. Processing a channel state storage instruction does not require the same amount of processing time as processing an SIO instruction, but it is necessary to synchronize the instruction processing between the instruction processor and the input/output processing device. requires a processing time that is about a fraction of that of an SIO instruction.

[0007]

By the way, as explained in the above-mentioned conventional technology, in processing a channel state storage instruction, the instruction processor starts executing the channel state storage instruction, and then the instruction processor and system control device , the hardware response is taken between the input/output processing devices to execute the command, so there is a problem that the time required to store the channel state and execute the command becomes long.

An object of the present invention is to store state information of channels connected to the input/output processing device on the main storage in a computer system consisting of an instruction processor, an input/output processing device, a system control device, and a main storage. An object of the present invention is to provide a channel state reading method that can process a channel state storage instruction at high speed.

[0009]

[Means for Solving the Problems] In order to achieve the above object, the channel state reading method of the present invention includes a system in which a plurality of instruction processors are connected to an input/output processing device having a plurality of channels via a system control device. In a computer system that has a main memory shared by each instruction processor and input/output processing device, a system-shared dedicated area is provided on the storage device that can be accessed by both the instruction processor and the input/output processing device, and the input/output processing device Channel state information is stored in the dedicated area at regular intervals, and when the instruction processor executes a channel state storage instruction, the channel state information stored in the dedicated area is read from the input/output processing device and stored in the main memory. It is characterized by performing processing for storing at a specified address.

0010

[Operation] According to this, a plurality of instruction processors are connected to an input/output processing device having a plurality of channels via a system control device, and a computer having a main storage device shared by each instruction processor and input/output processing device. In a system, a system-shared dedicated area is provided on a storage device that is accessible by both an instruction processor and an input/output processing device. The input/output processing device stores channel state information in the dedicated area at regular intervals, regardless of the operation of the instruction processor. In addition, when the instruction processor executes a channel state storage instruction, the channel state information stored in the dedicated area is read from the input/output processing device and stored at the specified address of the main storage device specified by the operand. I do.

In this way, a dedicated shared area for storing channel state information is provided, the input/output processing device and the instruction processor access the channel state storage shared area asynchronously, and the input/output processing device updates the channel state information at regular intervals. Information continues to be stored, and the instruction processor accesses the channel state storage shared area at any time to read out necessary channel state information.

[0012] As a result, when processing a channel state storage instruction, the instruction processor does not need to receive a response from the input/output processing device, and the instruction can be executed using only the processing time required to access the main memory, enabling high-speed processing. becomes.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a data processing system according to an embodiment of the present invention. In FIG. 1, 1 is an instruction processor (IP), 2 is a system control unit (SC), and 3 is an input/output processing unit (IOP). In addition, 4 is a plurality of channels (CH0 to CHm)
5 is the main memory (MS). As the system scale increases, a plurality of instruction processors 1 are provided.

A plurality of instruction processors 1, input/output processing devices 3, and main storage devices 5 are connected to each other via a system control device 2. Further, in the input/output processing device 3, a plurality of (m) channels 4 are connected. The storage areas of the main storage device 5 are a hardware system area (HSA) 5a and a software usage area (SU
A) It is divided into 5b and used. The hardware system area (HSA) 5a is a dedicated area for controlling hardware used only by the microprogram (firmware) of the instruction processor 1 and the input/output processing device 3, and the software use area (SUA) 5b is
This is a storage area used by software such as the operating system and user programs. The hardware system area (HSA) 5a is provided with a channel-like storage area 20, which is a dedicated area for storing channel state information.

FIG. 2 is a diagram showing an example of the configuration of a channel-shaped storage area provided in the hardware system area. As shown in the figure, in the channel storage area 20, channel condition bits (CH(m)/A bits) 21 indicating the channel state corresponding to each channel are allocated as many as the number of channels. When the channel status bit is “1”, it indicates that the channel is in operation, and when it is “0”, it indicates that the channel is not in operation, is in an inoperable state, or the channel is not in operation in the system. It shows that it doesn't exist.

In the data processing system configured as described above, the input/output processing unit (IOP) 3 examines the operating states of all the channels of each channel CH0 to CHm at regular time intervals, and Create channel state information in which bits indicating the operating state are assigned to each channel. The channel state information of each channel created is temporarily held in a register within the input/output processing device 3. After completion of this operation, the input/output processing device 3 stores the channel state information in the channel state storage area 20 provided in the hardware system area 5a in the same way as a normal storage operation in the main storage device 3.

On the other hand, when a channel state storage instruction is executed by the instruction processor 1, the microprogram checks the execution conditions of the channel state storage instruction, and if the execution conditions are satisfied, it is stored in the normal main memory. The channel state information stored therein is read out from the channel state storage area 20 by a process similar to the read operation. After the read process is completed, the read channel state information is written to the specified address on the main memory specified by the operand of the channel state storage instruction, and the instruction is executed after waiting for the write operation to complete. Complete the action.

As explained above, according to this embodiment, it is possible to execute a channel state storage instruction asynchronously by the processing of the instruction processor alone, completely independent of the operation of the input/output processing device, and the instruction processing can be executed. Processing can be performed at the same high speed as memory access processing.

[0019]

As explained above, according to the channel state reading method of the present invention, responses can be synchronized hardware-wise between an instruction processor, a system control device, and an input/output processing device, unlike the conventional method. Therefore, the channel state storage command can be processed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a data processing system according to an embodiment of the present invention;

FIG. 2 is a diagram showing a configuration example of a channel-shaped storage area provided in a hardware system area;

[Figure 3]
FIG. 3 is a block diagram showing the configuration of a computer system for explaining the processing of a conventional channel state storage command.

[Explanation of symbols]

1 Instruction processor (IP) 2 System control unit (SC) 3 Input/output processing unit (IOP) 4 Multiple channels (CH0 to CHm) 5
Main memory (MS) 5a Hardware system area (HSA) 5b
Software usage area (SUA) 20 Channel status storage area 21 Channel status bit

Claims (1)

[Claims] 1. A computer system in which a plurality of instruction processors are connected to an input/output processing device having a plurality of channels via a system control device, and a main storage device is shared by each instruction processor and the input/output processing device, comprising:
A system-shared dedicated area is provided on a storage device that can be accessed by both the instruction processor and the input/output processing device, and the input/output processing device stores channel state information in the dedicated area at regular intervals, and stores the channel state information of the instruction processor. A channel state reading method characterized in that, in executing a storage instruction, a process is performed in which channel state information stored in the dedicated area is read from an input/output processing device and stored at a specified address in a main storage device.