JPH01145758A - Time synchronizing system for multisystem computer system - Google Patents

Time synchronizing system for multisystem computer system

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Publication number
JPH01145758A
JPH01145758A JP62187945A JP18794587A JPH01145758A JP H01145758 A JPH01145758 A JP H01145758A JP 62187945 A JP62187945 A JP 62187945A JP 18794587 A JP18794587 A JP 18794587A JP H01145758 A JPH01145758 A JP H01145758A
Authority
JP
Japan
Prior art keywords
synchronization
computers
computer system
microcomputer
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62187945A
Other languages
Japanese (ja)
Inventor
Kazuyo Nakamura
中村 和世
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62187945A priority Critical patent/JPH01145758A/en
Publication of JPH01145758A publication Critical patent/JPH01145758A/en
Pending legal-status Critical Current

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  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To synchronize multisystem computer without generating a synchronizing request signal from each microcomputer by constituting the system so that plural computers are synchronized in a prescribed period at every loop program processing, based on a synchronizing signal of a synchronization use computer. CONSTITUTION:In a multisystem computer system which is provided with plural sets of computers 1, 2 and 3 and executes the same loop program, a synchronization processing use computer 4 is provided so that these computers 1, 2 and 3 can execute a synchronization processing of a prescribed period, and based on a synchronizing signal of this synchronization processing use computer 4, plural computers 1, 2 and 3 are synchronized at every loop program processing, and also, its loop program processing can be executed in a prescribed period. In such a way, the multisystem computer system can be synchronized without generating a synchronization request signal from each microcomputer 1, 2 and 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は複数のマイクロコンピュータを使ったプラン
トシステムにおける時刻同期に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to time synchronization in a plant system using a plurality of microcomputers.

〔従来の技術〕[Conventional technology]

第8図は例えば特開昭57−13565公報に示された
従来の多重系計算機システムを示す図である。
FIG. 8 is a diagram showing a conventional multi-system computer system disclosed in, for example, Japanese Unexamined Patent Publication No. 57-13565.

図において(4)は同期信号発生装置であり、LL) 
12) (3)はマイクロコンピュータである。
In the figure, (4) is a synchronization signal generator (LL)
12) (3) is a microcomputer.

次に動作について説明する。マイクロコンピュータ+1
1 、 (2) 、 (3)より同期要求信号qυ、c
!υ、 onが入力され、これらに基づいてマイクロコ
ンピュータill 、 +21 、 (3)に同期割込
信号(6)、す、−が出力される。
Next, the operation will be explained. Microcomputer +1
From 1, (2), and (3), the synchronization request signal qυ,c
! υ, on are input, and based on these, synchronous interrupt signals (6), s, - are output to the microcomputer ill, +21, (3).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の同期方式は以上のように構成されているのでマイ
クロコンピュータ+1) 、 +2) 、 (3)によ
る同期要求信号を入力しなければならず、また同期割込
信号を各々マイクロコンピュータに対し出力することが
必要なため各々のマイクロコンピュータの一巡プログラ
ムの実行周期が一定でないなどの問題点があった。
Since the conventional synchronization method is configured as described above, synchronization request signals from microcomputers +1), +2), and (3) must be input, and synchronization interrupt signals must be output to each microcomputer. Because of this, there were problems such as the execution cycle of each microcomputer's one-round program was not constant.

この発明は上記のような問題点を解消するためになされ
たもので割込信号を発生させることなく複数の計算機を
一定周期で同期がとられた計算機システムを得ることを
目的とする。
The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a computer system in which a plurality of computers can be synchronized at a constant cycle without generating an interrupt signal.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る計算機システムは複数台の計算機を有し
、同一の一巡プログラムを実行する多重系計算機システ
ムにおいてこれら計算機が一定周期の同期処理を行える
ように同期処理用計算機を設け、この同期処理用計算機
の同期信号をもとに複数の計算機が一巡のプログラム処
理ごとに同期がとられ、かつその−巡プログラム処理が
一定周期で行えるようにしたものである。
A computer system according to the present invention has a plurality of computers and is provided with a synchronous processing computer so that these computers can perform synchronous processing at a constant cycle in a multi-system computer system that executes the same one-round program. A plurality of computers are synchronized for each round of program processing based on a synchronization signal of the computers, and the round of program processing can be performed at a constant cycle.

〔作用〕[Effect]

この発明lこおける計算機システムは同期処理用計算機
及びその計算機と同期処理を行う複数台のマイクロコン
ピュータ及び同期信号を伝送する伝送路から構成される
The computer system in this invention is comprised of a synchronous processing computer, a plurality of microcomputers that perform synchronous processing with the computer, and a transmission path for transmitting synchronous signals.

〔発明の実施例〕 以下この発明の一実施例を図について説明する。[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

第1図において(4)は同期信号発生装置であり、(υ
In Fig. 1, (4) is a synchronization signal generator, (υ
.

+21 、 (3)は各々同一のプログラム処理をくり
返し実行するマイクロコンピュータ、(5)は同期信号
をマイクロコンピュータ(1)、 (2) 、 (3)
に送る伝送路である。
+21, (3) are microcomputers that repeatedly execute the same program processing, (5) are microcomputers (1), (2), (3) that use synchronization signals.
It is a transmission line for sending to.

同期信号発生装置(4)はマイクロコンピュータが内蔵
されており、一定周期で同期信号を送信するように処理
されている。
The synchronization signal generator (4) has a built-in microcomputer and is processed to transmit synchronization signals at regular intervals.

本同期信号(6)、i4a、aはマイクロコンピュータ
(υ、 +21 、 (3)からの同期要求信号を受け
とらず、同期信号発生装置常に一定周期で送信する。
The synchronization signals (6), i4a, and a do not receive synchronization request signals from the microcomputer (υ, +21, (3)), and are always transmitted by the synchronization signal generator at a constant cycle.

いま、各々マイクロコンピュータと同期信号発生装置に
電源が供給され処理がスタートしたとする。マイクロコ
ンピュータ(1) 、 (2) 、 (3)は第5図の
フローチャートのイニシャライズ処理συを行い、同期
信号発生装置(4)は第4図のフローチャートのイニシ
ャライズ処理(2)を行う。本イニシャライズ鴨即は、
マイクロコンピュータ内部のメモリクリア等、通常マイ
クロコンピュータシステムで行われる処理である。同期
信号発生袋@(4)はイニシャライズ処理(2)が終了
すると一巡プログラムの実行周期をきめるタイマー(6
)をリセットし本システムが一定周期で動作するように
する。
Assume now that power is supplied to the microcomputer and the synchronization signal generator, and processing has started. The microcomputers (1), (2), and (3) perform the initialization process συ shown in the flowchart of FIG. 5, and the synchronization signal generator (4) performs the initialization process (2) of the flowchart shown in FIG. This initialize Kamo Soku is
This is a process normally performed in a microcomputer system, such as clearing the memory inside the microcomputer. The synchronization signal generation bag @ (4) is a timer (6) that determines the execution cycle of the one-round program when the initialization process (2) is completed.
) so that this system operates at a constant cycle.

同期信号発生装置(4)はタイマーをもとに周期的に同
期信号を各々マイクロコンピュータ(υ、 (2) 。
The synchronization signal generator (4) periodically generates a synchronization signal to each microcomputer (υ, (2)) based on a timer.

(3)に送信する。各々マイクロコンピュータは第5図
のフローチャートのイニシャライズ処理(2)が終了す
ると同期信号発生装置t (4)より同期信号が送信さ
れるのを待つ。送信されてくるとただちにタイマーをリ
セットし一巡プログラムを実行する。
(3) Send to. When the initialization process (2) in the flowchart of FIG. 5 is completed, each microcomputer waits for a synchronization signal to be transmitted from the synchronization signal generator t (4). As soon as it is sent, the timer is reset and the round program is executed.

−巡プログラムの最後に周期時間であることをチエツク
し、また同期信号発生袋@(4)より同期信号が送信さ
れるのを待つ。
- Check that the cycle time is reached at the end of the cycle program, and wait for the synchronization signal to be sent from the synchronization signal generation bag @(4).

以上のように本計算機システムでは各マイクロコンピュ
ータ(1) 、 (2) 、 (3)よりの同期要求信
号を発生することなく多重系計算機の同期をとることが
できる。
As described above, in this computer system, multiple computers can be synchronized without generating synchronization request signals from each of the microcomputers (1), (2), and (3).

なお、上記実施例では同期信号発生袋A(4)及び伝送
路(5)を1重化構成としたが、第2図のように2重化
構成としてもよい。
In the above embodiment, the synchronizing signal generating bag A (4) and the transmission line (5) have a single configuration, but they may also have a double configuration as shown in FIG.

2重化構成とすることによって同期信号発生装置が2台
となることにより一台の同期信号発生装置が欠つンして
も同期信号がマイクロコンピュータu) 、 +2) 
、 (3)に送られることになり、より信頼性の高い同
期方法が得られる。
By adopting a duplex configuration, there are two synchronous signal generators, so even if one synchronous signal generator is lost, the synchronous signal can still be transmitted to the microcomputer u), +2).
, (3), providing a more reliable synchronization method.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば同期発生信号を各々のマ
イクロコンピュータからの同期信号要求信号なしに多重
系計算機システムの同期をとることができる。
As described above, according to the present invention, a multi-system computer system can be synchronized using a synchronization generation signal without requiring a synchronization signal request signal from each microcomputer.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この発明の一実施例の計算機システム構成図
、第2図は、この発明の他の実施例を示す計算機システ
ムの構成図、第8図は、従来の計算機システムの構成図
、第4図は、同期信号発生装置の同期処理を行うプログ
ラムのフローチャートであり、また第5図は、上記同期
信号に基づいて同期処理を行うマイクロコンピュータの
同期方式を示すフローチャートである。+13 、 (
21、(3)は同JEU(8号に基いて一巡のプログラ
ムをくり返し実行するマイクロコンピュータ、(4)は
同期信号発生装置、(5)は同期信号伝送路、(6)は
タイマーである。 なお、図中同一符号は同一、又は相当部分を示す。
FIG. 1 is a configuration diagram of a computer system according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a computer system showing another embodiment of the invention, and FIG. 8 is a configuration diagram of a conventional computer system. FIG. 4 is a flowchart of a program that performs synchronization processing of the synchronization signal generator, and FIG. 5 is a flowchart showing a synchronization method of a microcomputer that performs synchronization processing based on the synchronization signal. +13, (
21, (3) is a microcomputer that repeatedly executes a program based on JEU (No. 8), (4) is a synchronizing signal generator, (5) is a synchronizing signal transmission line, and (6) is a timer. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

【特許請求の範囲】[Claims] (1)複数台の計算機を有し同一の一巡プログラムを実
行する多重系計算機システムにおいて、これら計算機が
同期処理を行えるように同期処理用計算機を設け、同期
用計算機の同期信号をもとに複数の計算機が一巡のプロ
グラム処理ごとに一定周期で同期をとるようにしたこと
を特徴とする多重系計算機システムの時刻同期方式。
(1) In a multi-system computer system that has multiple computers and executes the same one-round program, a synchronous processing computer is provided so that these computers can perform synchronous processing, and multiple computers are A time synchronization method for a multi-system computer system, characterized in that the computers of the computer are synchronized at a constant cycle for each round of program processing.
(2)同期用計算機を2台設置しともに同期信号を発生
するようにし、より信頼性の高い同期がとれるようにし
たことを特徴とする多重系計算機システムの時刻同期方
式。
(2) A time synchronization method for a multi-system computer system, characterized in that two synchronization computers are installed and both generate synchronization signals, thereby achieving more reliable synchronization.
JP62187945A 1987-07-27 1987-07-27 Time synchronizing system for multisystem computer system Pending JPH01145758A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62187945A JPH01145758A (en) 1987-07-27 1987-07-27 Time synchronizing system for multisystem computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62187945A JPH01145758A (en) 1987-07-27 1987-07-27 Time synchronizing system for multisystem computer system

Publications (1)

Publication Number Publication Date
JPH01145758A true JPH01145758A (en) 1989-06-07

Family

ID=16214922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62187945A Pending JPH01145758A (en) 1987-07-27 1987-07-27 Time synchronizing system for multisystem computer system

Country Status (1)

Country Link
JP (1) JPH01145758A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713565A (en) * 1980-06-27 1982-01-23 Toshiba Corp Synchronizing method of multiprocessor computer system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713565A (en) * 1980-06-27 1982-01-23 Toshiba Corp Synchronizing method of multiprocessor computer system

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