JPH02270010A - Time synchronizing method for multiple computer system - Google Patents

Time synchronizing method for multiple computer system

Info

Publication number
JPH02270010A
JPH02270010A JP1092579A JP9257989A JPH02270010A JP H02270010 A JPH02270010 A JP H02270010A JP 1092579 A JP1092579 A JP 1092579A JP 9257989 A JP9257989 A JP 9257989A JP H02270010 A JPH02270010 A JP H02270010A
Authority
JP
Japan
Prior art keywords
synchronization
computers
devices
synchronizing
main
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1092579A
Other languages
Japanese (ja)
Inventor
Kazuyo Harada
原田　和世
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1092579A priority Critical patent/JPH02270010A/en
Publication of JPH02270010A publication Critical patent/JPH02270010A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To secure the synchronization among plural computers in a fixed cycle even though a synchronizing signal generating device has a trouble at its single side by preparing tow synchronizing computers and securing the synchronization among plural computers based on the synchronizing signal of the main one of both synchronizing computers. CONSTITUTION:When the initializing processes are through with the synchronizing signal generating devices 1 and 2, both devices 1 and 2 reset a timer 6 to decide the executing cycle of a single circulation program so that a main system works in a fixed cycle. The devices 1 and 2 are duplicated and the main one of both devices 1 and 2 is controlled by a transmission line 7 connecting both devices 1 and 2. Then the main device 1 or 2 transmits the synchronizing signals to microcomputers 31 - 34. Thus the synchronization is surely and accurately secured among plural computers.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は複数のマイクロコンピュータｋｆｅつたプラ
ント多重系計算機システムにおける時刻同期方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time synchronization method in a plant multiplex computer system including a plurality of microcomputers.

〔従来の技術〕[Conventional technology]

第４図は従来の多重系計算機システムの時刻同期方式を
示すブロック図で１図において、…Ｆｉ同期信号発生装
置、６υ〜ｃｎＶｉ各々同一のプログラム処理を実行す
るマイクロコンピュータ、１５）は同期信号をマイクロ
コンピュータＧ（１１−Ｃ１４に送る伝送路である。Fig. 4 is a block diagram showing the time synchronization method of a conventional multi-system computer system. This is a transmission line for sending to the microcomputer G (11-C14).

次に動作について説明する。同期信号発生装置１ｕ＋は
マイクロコンピュータが内蔵されておシ、一定周期で同
期信号を送信するように処理されている。Next, the operation will be explained. The synchronization signal generator 1u+ has a built-in microcomputer and is processed to transmit synchronization signals at regular intervals.

同期信号発生装置Ｉｌ＋はタイマー（６）をもとＶＣ＠
期的に同期信号を各々マイクロコンピュータＣ（υ〜（
ロ）に送信する。The synchronization signal generator Il+ generates VC@ based on the timer (6).
Periodically, the synchronization signal is sent to each microcomputer C(υ~(
b)).

各々マイクロコンピュータ（ｉｌｌ−■は同期信号発生
装置（１１より同期信号が送信されるのを待つ。Each microcomputer (ill-2) waits for a synchronization signal to be transmitted from the synchronization signal generator (11).

送信されてくるとただちにタイマー（６１をリセットし
、−巡プログラムを実行する。Immediately upon receiving the data, the timer (61) is reset and the cycle program is executed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の多重系計算機システムの時刻同期方式は以上のよ
うに構成されていたので、同期発生装置が故障した場合
マイクロコンピュータに同期信号が送信できなくなり、
マイクロコンビュ−夕は同期信号発生装置からの信号を
受信できずまた、ＡＵ、７３７５８　Ｋ述べられている
ように２台の同期信号発生装置を設けても２台の装置の
どちらからの信号を受は取るのがマイクロコンピュータ
側が判別できないという問題点があった。The conventional time synchronization method for multiple computer systems was configured as described above, so if the synchronization generator failed, the synchronization signal could no longer be sent to the microcomputer.
The microcomputer cannot receive the signal from the synchronization signal generator, and as stated in AU, 73758K, even if two synchronization signal generators are installed, it cannot receive the signal from either of the two devices. There was a problem that the microcomputer could not determine which one was taken.

この発明は上記のような問題点を解消するためになされ
たもので、同期信号発生装置の片側が故障しても複数の
計算機を一定周期で同期を取ることができる多重系計算
機システムの時刻同期方法を得ることを目的とする。This invention was made to solve the above-mentioned problems, and it provides time synchronization in a multi-system computer system that allows multiple computers to be synchronized at a constant cycle even if one side of the synchronization signal generator fails. The purpose is to obtain a method.

〔諌題を解決する之めの手段〕[Means to solve the problem]

この発明に係る多重系計算機システムの時刻同期方法は
複数台の計算機を有し、同一の一巡プログラムを実行す
る多重系計算機システムにおいてこれら計算機が一定周
期の同期処理を行えるように同期用計算機を２台設け、
この２台の同期用計算機の内生系である同期用計算機の
同期信号をもとに、複数の計算機が一巡のプログラム処
理ごとに一定周期で同期をとるようにしたものである。The time synchronization method for a multi-system computer system according to the present invention is such that in a multi-system computer system that has a plurality of computers and executes the same one-cycle program, two synchronization computers are used so that these computers can perform synchronization processing at a constant period. Set up a stand,
Based on the synchronization signal of the synchronization computer which is an endogenous system of these two synchronization computers, a plurality of computers are synchronized at a constant cycle for each round of program processing.

〔作用〕[Effect]

この発明における２台の同期用計算機は２台の同期信号
発生装置の内の主系より送られた同期信号をもとに同期
処理を行い、この同期信号全同期信号発生装置間を伝送
する伝送路により管理するようにしたので、複数の計算
機の同期を確実正確にとることができる。The two synchronization computers in this invention perform synchronization processing based on the synchronization signal sent from the main system of the two synchronization signal generators, and transmit this synchronization signal between all the synchronization signal generators. Since the computer is managed by the computer, multiple computers can be synchronized reliably and accurately.

〔実施例〕〔Example〕

以下、この発明の一実施ＰＩ　ｋ図について説明する。 Hereinafter, a PI k diagram according to an embodiment of the present invention will be described.

第１図において、Ｉｌｌ　、　＋２１は同期信号発生装
置であり、（ロ）〜（ロ）は各々同一のプログラム処理
をくり返し実行するマイクロコンピュータ、＋５１　ｎ
　？イクロコンピュータ６υ〜（至）に同期信号を送る
伝送路である。In FIG. 1, Ill and +21 are synchronizing signal generators, (b) to (b) are microcomputers that repeatedly execute the same program processing, and +51 n
? This is a transmission line that sends a synchronization signal to the microcomputer 6υ.

同期信号発生装置＋１１　、１２１にはマイクロコンピ
ュータが内蔵されており、一定周期で同期信号を送信す
るように処理されている。The synchronization signal generators +11 and 121 have built-in microcomputers, and are processed to transmit synchronization signals at regular intervals.

この同期信号■、ｄ、（４１，■は同期信号発生装置ｆ
ｉｌ　１２１の内、どちらか一方から発信きれる。それ
は同期信号発生装置）旧２）間の伝送路（７）によって
同期信号発生装置間でどちらが同期信号を発信するかを
管理されている。These synchronizing signals ■, d, (41, ■ are the synchronizing signal generator f
You can make a call from either one of il 121. The transmission path (7) between the synchronizing signal generators) and old 2) controls which of the synchronizing signal generators will transmit the synchronizing signal.

次に動作について説明する・ いま、それぞれのマイクロコンピュータ６Ｄ−■と同期
信号発生装置１１１　＋２１に電源が供給され処理がス
タートしたとする。マイクロコンピュータ６１）〜ｃ３
４は第３図のフローチャートのイニシャライズ処理（７
υを行い、同期信号発生装置は第３図のフローチャート
のイニシャライズ処理−７０を行う。このイニシャライ
ズ処理（１１１はマイクロコンピュータ内部のメモリク
リア等、通常のマイクロコンピュータ７ステムで行われ
る処理である。Next, the operation will be explained. Assume that power is supplied to each of the microcomputers 6D-1 and synchronous signal generators 111+21, and processing has started. Microcomputer 61) ~ c3
4 is the initialization process (7
υ is performed, and the synchronizing signal generator performs the initialization process-70 in the flowchart of FIG. This initialization process (111 is a process performed by a normal microcomputer 7 system, such as clearing the memory inside the microcomputer).

同期信号発生装置＋ｌｌ　、　！２１は第２図のようＶ
Ｃイニシャライズ処理・、ｌＩｌが終了すると、−巡プ
ログラムの実行周期を決めるタイマー（６）ラリセット
し、本システムが一定周期で動作するようにする。Synchronous signal generator+ll, ! 21 is V as shown in Figure 2.
When the C initialization process is completed, the timer (6) that determines the execution cycle of the -cycle program is reset, so that the system operates at a constant cycle.

周期信号発生装置中（２）は２直化されており、それら
の装置間を結ぶ伝送路（７１により、どちらが主系であ
るかを管理し、主系であるどちらか一方の同期信号発生
装置１１１１２１が同期信号をマイクロコンピュータ６
υ〜鏝に送信する。The middle periodic signal generator (2) is a two-channel system, and a transmission line (71) that connects these devices manages which one is the main system. 111121 sends the synchronization signal to microcomputer 6
Send to υ~ trowel.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、同期用計算機を２台設
け２台のうち主系である同期用計算機の同期信号をもと
に複数の計算機の四Ｍをとるように構成したので、より
精度の高い多重系計算機システムの時刻同明方法が得ら
れる効果がある。As described above, according to the present invention, two synchronization computers are provided and the 4M of the plurality of computers is determined based on the synchronization signal of the main synchronization computer of the two, so that This has the effect of providing a highly accurate time identification method for a multi-system computer system.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実ＦＭ例による多重系計算機シス
テムの１を改ブロック図、第２図はこの発明の一実施例
である同期信号発生装置側の処理を示すフローチャート
、第３図は同じく同期信号を受信するマイクロコンピュ
ータ側の処理を示すフローチャート、第４図は従来の多
重系計算機システムの１ｌｌｊブロック図である。 図中、１１１　、１２１は同期信号発生装置、Ｃ（む情
は同期信号を受信するマイクロコンピュータ、（財）〜
（４４は同期信号、（６）はタイマー、（７１は同期信
号発生装置＋１１　＋２１間の伝送路を示す。 なお、図中、同−符５＋ハ同一、又は相当部分子ｚｒ：
示す。FIG. 1 is a revised block diagram of a multi-system computer system according to an FM example of the present invention, FIG. 2 is a flowchart showing processing on the side of a synchronization signal generator which is an embodiment of the present invention, and FIG. Similarly, FIG. 4 is a flowchart showing processing on the side of a microcomputer that receives a synchronization signal, and is a block diagram of a conventional multi-system computer system. In the figure, 111 and 121 are synchronization signal generators, C (indicates a microcomputer that receives synchronization signals, and
(44 is a synchronization signal, (6) is a timer, (71 is a transmission path between synchronization signal generators +11 and +21.
show.

Claims (1)

【特許請求の範囲】[Claims] （１）複数台の計算機を有し同一の一巡プログラムを実
行する多重系計算機システムにおいて、これら計算機が
同期処理を行えるように同期用計算機を２台設け、この
２台のうち主系である同期用計算機の同期信号をもとに
、複数の計算機が一巡のプログラム処理ごとに一定周期
で同期をとるようにしたことを特徴とする多重系計算機
システムの時刻同期方法。(1) In a multi-system computer system that has multiple computers and executes the same one-cycle program, two synchronization computers are provided so that these computers can perform synchronization processing, and the main system among these two computers is synchronized. A time synchronization method for a multi-system computer system, characterized in that a plurality of computers are synchronized at a constant cycle for each round of program processing based on a synchronization signal of a computer.
JP1092579A 1989-04-12 1989-04-12 Time synchronizing method for multiple computer system Pending JPH02270010A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1092579A JPH02270010A (en) 1989-04-12 1989-04-12 Time synchronizing method for multiple computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1092579A JPH02270010A (en) 1989-04-12 1989-04-12 Time synchronizing method for multiple computer system

Publications (1)

Publication Number Publication Date
JPH02270010A true JPH02270010A (en) 1990-11-05

Family

ID=14058342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1092579A Pending JPH02270010A (en) 1989-04-12 1989-04-12 Time synchronizing method for multiple computer system

Country Status (1)

Country Link
JP (1) JPH02270010A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109459964A (en) * 2017-09-06 2019-03-12 张勇 Plesichronous automatic running controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109459964A (en) * 2017-09-06 2019-03-12 张勇 Plesichronous automatic running controller

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