JPS58140840A - Baud rate controller - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution and to reduce the area of a board for a device using a programmable timer, by facilitating the setting of the baud rate with a change of software. CONSTITUTION:A microprocessor 2 changes the initial set value of a register in a programmable timer module 1 on the basis of the software stored in a memory 3. As a result, it is possible to deliver a signal phiout which is obtained by dividing an enable signal phiE or clock signal phiC down to an appropriate frequency. This signal phiout is used for a serial I/O interface 5 as a data transfer signal between an input/output device 6 and the interface 5. This facilitates the setting of the baud rate with a change of the software. As a result, the circuit constitution is simplified with a reduced board area.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a baud rate control system using a 1c1 grammar pull timer (hereinafter abbreviated as 2-cho M).

91, t c. Convert the parallel data signal sound sent from the microprocessor MPU into a serial data signal, and output serial signals such as ORτ II! KX! ! 9, or reverse K, serial signal t manually input from input/output equipment
In the serial interface for converting into parallel signals, the setting of the baud rate (transfer speed f) during signal transfer is generally performed by a clock frequency divider circuit using a counter consisting of a flip-flop.

However, with this Serial E10 interface,
It is necessary to change the baud rate depending on the type of human output device connected.

Changes in baud rate in this case! ! Conventionally, this has been done by connecting to the output sound jumper terminal of the clock frequency dividing circuit and switching the jumper m connected to the serial X, /O interface using hardware.

By the way, the baud rate is approximately 110 to 19
The 11Ii, which is popular within a relatively wide range of 200BFB (bits per second) equipment, has been selected and has been defeated.

Therefore, K, which makes it possible to select any baud rate within the above range, requires a complicated and large frequency divider circuit, and requires a large number of jumper terminals. Inconveniently, the area of the attached board is also increased. The baud rate changes depending on the input/output m (transition), but if you switch it in a hardware way with a jumper every time, it will be difficult to use.

Therefore, according to the invention, the frequency of the enable signal is divided by 7t using an internal register, or the enable signal is counted by t and the signal is sampled by t, in response to a command from a microprocessor or the like. By using PTMI that can output, baud rate communication on serial interfaces, etc. In order to be able to set it, J) C is assumed to be one.

This Gakumeikai will be explained below using Figure 1.

亦tVa, - as serial I10 interfney jIKtIP volley) ti'? The block configuration of one path for setting Ml is shown.

Actually 211iiiifIl'tsni, P T M l t”
Iku' 7 o * t (hereinafter abbreviated as MPU) 2 is the address line. ~m, and data bus D,
~D! are connected by. In addition, MPU2 has
A memory 3 in which software for operating the r& is stored is connected.

A chip select signal is formed by defooding the binary signal output from the MPU 2 by the decoder 4, and the area constituting PTM 1 in the L8 chip is selected by the chip select signal.

An enable signal φ is applied to PTMl from outside the chip.

When the chip is selected, the PTMI is enabled by the enable signal -8. Makhi, α clock qi number φ to PTMI
. is entered.

When the gate terminal Gi of PTMl is fixed at a low level, terminals 01 and 10 gates are opened and the clock signal φ is
. And the enable signal φ, or the output signal inside the PTMI? Is there a plurality of registers built into the PTMI? , the register is selected by the address signals t17t outputted from the MPU2.

Then, depending on the content (initial setting) K of the selected register, the enable signal φ or directly frequency-divided signals of m* number of 1a are outputted from the output terminal 01. Alternatively, depending on the initial settings of the register, enable signals φ, t
Count and clock signal φ. By sampling, a signal of 4IA j# wave number is output from the output terminal 01. In other words, the MPU 2 initializes the registers inside the PTMI according to the software stored in the memory 3 via the data buses D, to D1.

The enable signal φ is estimated one by one from the setting line of the gK register, and when the register becomes zero,
Clock signal φ. I'm going to sample the meeting. As a result of this/14C, the output gI-8U or high level'*7t is reduced to low level. In addition, the register t that became a mess
The original initial setting value is written into the ISO buffer within lfPTM. By repeating this operation once, the output signal φ with an excessive frequency such as 19200Hg
. , is output.

The above output signal φ. u t Q) Memory 3 to J'll wavenumber
If the software tt' stored in the PTM is further changed to the initial setting 1i1' of the register inside the PTM, an arbitrary frequency can be set.

10,000, PTMI output signal φ. ut”, serial I10
Interface 5Kf5. Parallel data signals a, % (1,
. The data are serially transferred one by one to the input/output device 6 such as ORT by Ut, and then the data are studied.

That is, the output signal φ of PTMI. , but serial number 1
The output signal φ serves as a transfer signal for data transfer between the 0 interface 5 and the input/output device 6. Ut) 111
111 number or baud rate.

17t, a register initialized by %MPU2K is also built into the serial interface 5. The interface 5 receives the signal φ according to the initial setting of this register. utt - Use as is or signal φ. The frequency is divided into uttN, tIIil/16, or 1/64, and the data is transferred to the output device II6 by using the tie construction of No. 1.

Since this generator IJlj is configured as explained above, it can be changed to the enable signal or clock signal by changing the initial setting value of the register inside the PTM by changing the software V stored in the memory. This can be done by increasing the number of waves up to an excessive Ws wave number and outputting nine signals.

Then, data transfer (if(1) is used at this signal tone serial I10 interface equal pressure, so
The baud rate can be easily set by changing the software. Tsume 9, conventional counter 1r Kawagome Ω
Even though the baud rate changes to 1r like the Tsuk9 rope circuit,
There is no need for a jumper terminal on the mountain side or a hardware switchover. Therefore, the circuit configuration is simple and the board area can be reduced. 17t, it becomes possible to set the desired baud rate over a wide range of songs.

Easy drawing #! 1tBA FIG. 1 is a block W# diagram showing an embodiment of the baud rate control circuit according to the present invention.

DESCRIPTION OF SYMBOLS 1...Programmable timer module, 2...Microprocessor, 5...Data transfer flat film (IJ)
Flue 10 interface), 6...I/O device-1
φ. . . . Rack signal, φ, . . . Enable signal.

Agent Patent Attorney Usui 1) Rishizuku

Claims (1)

[Claims] The signal tone of the desired jIi1 wave number is obtained by filling at least one register in which data for determining the nine pigeon ratios is set, and dividing the frequency of the input clock signal by the division ratio t corresponding to the data set in the register. It is equipped with a programmable timer to output and a data transfer means whose timing of data transfer is controlled by the signal output from the programmable timer, and the data transfer means to be set in the register is changed by the software of the data processing microprocessor. By doing this, the baud rate in the data transfer 1sWP leg can be set to a desired value.Baud rate control IIT value as t% image.