JPS6467667A - Common bus arbitrating circuit - Google Patents

Abstract

PURPOSE:To prevent the collision of plural data on a system bus and to prevent the bus from being locked by executing the arbitration of bus using allowance in a system in which a bus requesting signal from plural bus masters is outputted asynchronously to a system clock. CONSTITUTION:The bus requesting signal, which is outputted by the respective bus masters, is fetched by a latch means 1 to be operated asynchronously to a clock, which is not-synchronized to the system clock outputted by a clock generating circuit 2. An arbitrating means receives the bus requesting signal fetched by the latch means 1 and executes the arbitration based on a prescribed priority. Then, a bus using allowing signal is outputted to one bus master based on the priority out of the bus masters to output the bus requesting signal. Thus, it is system that the bus requesting signal from the plural bus masters is outputted asynchronously to the system clock, even when a bus request is successively generated in a small time difference, plural data does not collide on the system bus. Even when some trouble is generated to the inverse of BUSY signal which is the control signal of a common bus, the bus is prevented from being locked.