JPS6472253A - Bus arbiter circuit - Google Patents

Abstract

PURPOSE:To ensure the even application of a bus among bus masters of the same priority order by giving the bus application permission signals with preference to the bus masters except the one that received the bus application permission signal last when plural bus request signals are received at one time. CONSTITUTION:The bus request signals RQ1-RQn which are synchronous with a common system clock pulse are received from plural bus masters 20-50 connected to a bus 70. One of these bus masters that delivered the signals RQ1...RQn is selected and the bus application permission signals AK1-AKn are applied to the selected bus master. A working bus master memory part 2 stores the bus master that received the permission signal last. Then a bus application permission generating part 1 recognizes the contents of the part 2 and gives the permission signals with preference to the bus masters except the one received the permission signal last in case plural bus request signals are received. Thus the bus masters of the same priority order can use evenly the bus 70.