JPS54149439A - Sequence control circuit - Google Patents

Sequence control circuit

Info

Publication number
JPS54149439A
JPS54149439A JP5716078A JP5716078A JPS54149439A JP S54149439 A JPS54149439 A JP S54149439A JP 5716078 A JP5716078 A JP 5716078A JP 5716078 A JP5716078 A JP 5716078A JP S54149439 A JPS54149439 A JP S54149439A
Authority
JP
Japan
Prior art keywords
address
repeat
circuit
register
selector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5716078A
Other languages
Japanese (ja)
Other versions
JPS5732816B2 (en
Inventor
Kazuyoshi Matsuhiro
Masaaki Yano
Yasunori Ouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5716078A priority Critical patent/JPS54149439A/en
Publication of JPS54149439A publication Critical patent/JPS54149439A/en
Publication of JPS5732816B2 publication Critical patent/JPS5732816B2/ja
Granted legal-status Critical Current

Links

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To obtain a sequence control circuit which can execute address increment for a repeat register, a repeat modification circuit and a repeat selector for the repeat processing.
CONSTITUTION: In case that an address is increased simultaneously with address modification, the output of address selection circuit 3 is supplied to repeat modification circuit 10 through the third selector 9. Consequently, the result obtained by modifying contents of the output of circuit 3 is stored in repeat register 8 simultaneously with storing the output of circuit 3 in address register 4. Here, register 8 is connected to address selection circuit 2 through the second selector 6 previously. Then, contents of register 8 can be modified and stored again independently of address generation by signal bus 24.
COPYRIGHT: (C)1979,JPO&Japio
JP5716078A 1978-05-16 1978-05-16 Sequence control circuit Granted JPS54149439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5716078A JPS54149439A (en) 1978-05-16 1978-05-16 Sequence control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5716078A JPS54149439A (en) 1978-05-16 1978-05-16 Sequence control circuit

Publications (2)

Publication Number Publication Date
JPS54149439A true JPS54149439A (en) 1979-11-22
JPS5732816B2 JPS5732816B2 (en) 1982-07-13

Family

ID=13047804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5716078A Granted JPS54149439A (en) 1978-05-16 1978-05-16 Sequence control circuit

Country Status (1)

Country Link
JP (1) JPS54149439A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5374331A (en) * 1976-12-13 1978-07-01 Rca Corp Macro command executing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5374331A (en) * 1976-12-13 1978-07-01 Rca Corp Macro command executing system

Also Published As

Publication number Publication date
JPS5732816B2 (en) 1982-07-13

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