JPS59163640A - Data processing system - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution and to realize the miniaturization of a data processor by storing a microprogram and its low-order program to the same control memory, and using a part of an address producing circuit for control memory in common with both programs. CONSTITUTION:Both a microprogram and a nano program are stored to a control memory 16 of a data processing system, and a multiplexer 22 is connected to the memory 16 via a control memory address line 13. At the same time, both programs share a program counter 20 and a parity checking circuit 24. While a microinstruction register 17 and nano instruction registers 18-1 and 18-2 are connected to the memory 16 via a control memory data line 14, and an instruction output line address bus 28 is connected to registers 17 and 18-1 and 18-2, respectively. Then both programs are carried out. Thus it is possible to simplify the data processing system and to miniaturize a data processor.

Description

[Detailed Description of the Invention] (A) Technical Field of the Invention The present invention relates to a data processing system2, and in particular, to a control storage device storing microprograms that stores programs with different properties and controls. , relates to a microprogram control method for executing and controlling these different programs.

1 (b) Conventional technology and problems ζ Conventional microprogram control method - G!
For programs with different properties and controls, a control unit 1q device (ROM), a control circuit, a counter, etc. are installed and operated individually. Even if the number of bits is small, a ROM with a capacity equal to the bit length is required, and check circuits such as parity checks are also required individually, which has the drawback of complicating the circuit with a large amount of logic.

In the configuration shown in FIG. 1, a central processing unit and an additional unit are provided, and the additional unit includes a floating point arithmetic unit, a decimal unit y1.
There are mechanisms, functional operation mechanisms, etc. In order to perform high-speed processing, these additional devices require microinstructions exclusively for that additional device. However, if all functions are added to the microprogram, the bit length per word will increase.

Therefore, the attached device has a program for i and +7 for each attached device under the control of the microprogram (this program is temporarily defined as a nanoprogram, and the instructions executed by the nanoprogram are hereinafter referred to as NQ commands). The bit length per word is kept to a minimum.

FIG. 2 is a diagram showing a conventional control system, in which 1 and 10 are control storage devices, 2 and 8 are adders, 3 and 9 are program counters, 4 is a stack, 5 is a multiplexer, and 6
and 12 are parity check circuits, 7 is a microinstruction register, and 11 is a nano (N) instruction register.

In the conventional system shown in FIG.
0 and the circuit that controls it are 1. It is divided into a microprogram control section and a nanoprogram control storage section, each of which is controlled individually. Therefore, as described above, this has the disadvantage that the amount of hardware increases.

(c) Purpose of the Invention An object of the present invention is to simplify the circuitry of a microprogram-controlled data processing device having a hierarchical structure.

(d) Structure of the Invention In order to achieve the object (4), the present invention provides at least a control storage device as well as a microb. The present invention is characterized in that a part of the address generation circuit is shared by the Dobe Microprogram and its lower level program 1:1, and is configured to execute the MicroProgera J and its 10th program.

(E) Embodiment of the Invention FIG. 3 is a diagram showing a control method of an embodiment of the present invention. Regisque, 16
is the control unit 1. a device, 17 is a micro (M) instruction register, 18---1, l 8----2 is a nano (N
) instruction register, 19 an adder, 20 an I-gram counter, 21 a stack, 22 a multiplexer,
2: (is a decoder, 24 is a parity check time (Raku).

Zero addition devices 0 to n are additional devices for floating point hI arithmetic processing, I (additional devices for l-ary arithmetic processing, function 8!
It consists of various equipment such as processing equipment.

A program counter (PCT) 20° and a parity check circuit (PC) 24 are commonly used.

The operation of the embodiment is as follows.

Based on the microphone 1 command stored in the operation register (OPR) 15, the microphone 1 coprogram J shown in FIG. 5(C) is executed according to the time charts 1 to 1 shown in FIG.
・The nanoprogram is executed.

In FIG. 4, clocks 01 to C18 are Jj! of the central processing unit. There is only one clock, and each timing is controlled. The T I, i' 2 signal is a microinstruction (M
Command) For practical control, NT1. The NT2 signal is used for controlling the execution of N instructions.

The microinstruction stored in 0PR15 in FIG. 1.1 Data is output to the data bus 14, and after parity check by the parity check circuit (PC) 24, the CI shown in FIG.
and T2 timing de M instruction register 7 in Figure 5 (C
) MPa command is sent. The program storage method (PCT) 20 is +1 and 0 in the adder' (INT) 19.
401 (hexadecimal).

During the execution of the MPa instruction, the value of PCT20 is the control record 1. It is output to the q address line 13, and the next M instruction, the MPb instruction, is set in the M instruction register 7 at the timing of C3 and '■'2. And at the same timing, PCT20
"+1 is added through C19 and 0402 (hexadecimal) is set. Thereafter, the next M instruction is read out in the same manner.

Termination of one M instruction is performed in two timings.

Next, execution of an MPC instruction will be explained.

Assume now that the MPc microinstruction format is the ExternalOut (EXO) format shown in FIG. 5(a). This command is exclusive to the additional device, and is used to start up the nano program or to transfer data between the central processing unit and the additional device.

When the MPc instruction is transferred to the M instruction register register, M
The lower bit A of the instruction register 7 is the multiplexer 22
The Naki program address at address 0010 (hexadecimal) is output to the control storage address line 13 through
h) be done.

Furthermore, the NTI and NT2 signals that control the N instruction are output to the control storage data bus 14, and the parity-checked data is sent to the N instruction register 8-- at timings 06 and NT2.
The NPa instruction is sent to 1 and execution begins.

Note that the contents of the control storage address line 13 are +1 through INC19, and 0011 (hexadecimal) is sent to PCT2O, C6
is set at the NT2 timing and starts reading the next N instructions.

The N command is composed of 2:3 bits as shown in FIG. 5(h), and only the necessary portion of the data output from the control storage device 16 is set.

The execution of one instruction ends at the N T2 timing, and the end of the nanoprogram is determined by the END bit of the instruction format (Fig. 5 f).
This is done by setting b1 (illustrated) to II II II.

Also, the same bit may be set to 1'1''' while the nanoprogram continues, and set to IT OII at the end of the program.
] It is also possible to use the END instruction as one nanoinstruction without providing a bit.

During the execution of the NPa instruction, the control storage address line 13 is
The content 0011 (hexadecimal) of CT 20 is output. N
N instructions are executed sequentially from the Pa instruction, and when execution starts at the N1) d instruction, the NPd instruction has the R-R format shown in FIG.
II, this command terminates NanoProgera J. A T2 signal is generated by the C14 clock, and the contents 0/103 (hexadecimal) of 5TKO in the stack 21 are popped (I) OP) and output to the control storage address line 113 through the multiplexer 22. Next order M due to dirt
Pd is output to the control storage data bus 14, and the M'Pd instruction is stored in the M instruction register 17 at the C14 and ]2 timing, and the process returns to execution of the microprogram. and MPd
, MPe instructions are executed sequentially, and the execution of one macro instruction is completed.

As described above, a microprogram control system is created in which microprograms with different properties and control formats can be stored in one control storage device, and programs can be easily switched from microprogram to nanoprogram and then back to microprogram. Realized.

FIG. 6 is a diagram showing another control system according to the present invention, and in the figure, the same numbers as in FIG. 3 indicate the same names.
28 is an instruction output line address bus.

The difference from the embodiment shown in FIG. 3 is the method of storing the program in the control storage device 25 and the addition of a command output line address line 28.

In this embodiment, the additional device Δ, 13 naps 1"
By sharing the same address in the control memory and sharing the length of the via 1, it is possible to share the connector pins.

(F) The nest of the invention According to the present invention, programs with different properties and control formats can be stored in one control storage device, and programs can be easily changed, making the logic much simpler than before. Therefore, it is possible to realize a compact, high-speed data processing device with a low 1dli rating.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of the configuration of a data processing device having a plurality of additional devices, and Fig. 2 is a diagram showing a conventional control system.
, FIG. 3 is a diagram showing the control system of the embodiment according to the present invention, FIG. 4 is a diagram showing the control method of the embodiment shown in FIG. Figure 5 shows an example (C1 is a diagram showing an example of a program arrangement in a control storage device, and Figure 6 is a diagram showing a control method of another embodiment according to the present invention. In the figure,] 3 is a control 14 is a control storage data line, 15 is an operation register. 16 is a control storage device, 17 is a my'/1co (M) instruction register, 18-1. 18-2 is a nano (N ) Outside the instruction register 19 is the adder, 20 is the program counter,
21 is a stack, and 22 is a multiplexer. 23 is a decoder, and 24 is a parity check circuit. 1 day l'l:l''〈Palace11iI'm,ノ)ノJ Xiaozhao ((1S&j1''昌1.'1-Button No., ?88 sentence δ)J
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Claims (5)

[Claims] (1) In a data processing device equipped with a microprogram and a lower-level program operating under the control of the microprogram, the microprogram and its lower-level program are stored in the same control program, and At least control storage address creation ITj
A data processing system characterized in that a part of llh is shared by the microprogram and its lower-level programs, and the ±8C microprogram and its lower-level programs are executed. (2) The lower level program is provided in the data processing device to execute arithmetic processing (a program dedicated to one device per device). method. (3) The above-mentioned additional device includes an additional device for floating point arithmetic processing, an additional device for decimal arithmetic processing, and an additional device for Kanto) arithmetic operation (2).
) Data processing method described in section. (4) When executing the lower-level program, the instructions of the lower-level program are read into instruction register means of a specified additional device. or the data processing method described in paragraph (3). (5) Claims (2) to (4) characterized in that the lower program instructions for a plurality of different additional devices are stored at the same address of the control device.
The data processing method described in any one of the above.