JPS56135243A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS56135243A
JPS56135243A JP3748980A JP3748980A JPS56135243A JP S56135243 A JPS56135243 A JP S56135243A JP 3748980 A JP3748980 A JP 3748980A JP 3748980 A JP3748980 A JP 3748980A JP S56135243 A JPS56135243 A JP S56135243A
Authority
JP
Japan
Prior art keywords
devices
geop
microinstructions
same time
increase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3748980A
Other languages
Japanese (ja)
Other versions
JPS6226487B2 (en
Inventor
Masahiro Hashimoto
Takaaki Nishiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3748980A priority Critical patent/JPS56135243A/en
Publication of JPS56135243A publication Critical patent/JPS56135243A/en
Publication of JPS6226487B2 publication Critical patent/JPS6226487B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To increase a processing speed in a plurality of arithmetic units and a plurality of microinstruction means which control said units by starting those microinstruction means at the same time. CONSTITUTION:Control storage 12 which controls floating-point arithmetic device F5, and control storage 14 which controls fixed-point arithmetic device G4 are provided. Two microinstructions of devices G and F are given processing end bits GEOP and FEOP, and when bits EIP appear, information fetch from instruction decoder I to the corresponding devices is controlled. On the other hand, only bit GEOP is provided with the capability of controlling the completion of instruction fetch to device I and interruption. Thus, microinstructions of devices 4 and 5 are started at the same time to increase the processing speed.
JP3748980A 1980-03-26 1980-03-26 Microprogram controller Granted JPS56135243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3748980A JPS56135243A (en) 1980-03-26 1980-03-26 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3748980A JPS56135243A (en) 1980-03-26 1980-03-26 Microprogram controller

Publications (2)

Publication Number Publication Date
JPS56135243A true JPS56135243A (en) 1981-10-22
JPS6226487B2 JPS6226487B2 (en) 1987-06-09

Family

ID=12498926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3748980A Granted JPS56135243A (en) 1980-03-26 1980-03-26 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS56135243A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59163640A (en) * 1983-03-09 1984-09-14 Panafacom Ltd Data processing system
JPS6349843A (en) * 1986-08-18 1988-03-02 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Reduction instruction set computer
JPH01310445A (en) * 1988-06-08 1989-12-14 Nippon Telegr & Teleph Corp <Ntt> Parallel arithmetic processor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5168749A (en) * 1974-12-11 1976-06-14 Fujitsu Ltd
JPS5479533A (en) * 1977-12-07 1979-06-25 Nec Corp Data processing unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5168749A (en) * 1974-12-11 1976-06-14 Fujitsu Ltd
JPS5479533A (en) * 1977-12-07 1979-06-25 Nec Corp Data processing unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59163640A (en) * 1983-03-09 1984-09-14 Panafacom Ltd Data processing system
JPS6349843A (en) * 1986-08-18 1988-03-02 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Reduction instruction set computer
JPH01310445A (en) * 1988-06-08 1989-12-14 Nippon Telegr & Teleph Corp <Ntt> Parallel arithmetic processor

Also Published As

Publication number Publication date
JPS6226487B2 (en) 1987-06-09

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