JPS5790733A - Bus controlling system - Google Patents

Bus controlling system

Info

Publication number
JPS5790733A
JPS5790733A JP16654780A JP16654780A JPS5790733A JP S5790733 A JPS5790733 A JP S5790733A JP 16654780 A JP16654780 A JP 16654780A JP 16654780 A JP16654780 A JP 16654780A JP S5790733 A JPS5790733 A JP S5790733A
Authority
JP
Japan
Prior art keywords
switches
line
controller
bus line
controlling system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16654780A
Other languages
Japanese (ja)
Inventor
Toshiaki Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16654780A priority Critical patent/JPS5790733A/en
Publication of JPS5790733A publication Critical patent/JPS5790733A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To reduce the transfer time of data, by controlling a switch provided to a bus line which is connected in common to plural logic blocks and then ensuring the use of the bus line after dividing it in terms of the space. CONSTITUTION:Switches 11 and 12 are provided to a bus line 101 which is connected in common to plural logic blocks 1-5. Then the line 101 is divided in terms of the space by controlling the switches 11 and 12. Thus the line 101 can be used. For instance, the the switches 11 and 12 are inserted to the line 101 as shown in the diagram, and a switch controller 10 is provided to control ON/ OFF of these switches. Control lines 201 and 202 are connected to the switches 11 and 12 through the controller 10. The switches 11 and 12 are controlled by the controller 10 by turning on and off based on the prescribed sequence or in accordance with the state of the system at that moment (such as a program control) and other methods.
JP16654780A 1980-11-28 1980-11-28 Bus controlling system Pending JPS5790733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16654780A JPS5790733A (en) 1980-11-28 1980-11-28 Bus controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16654780A JPS5790733A (en) 1980-11-28 1980-11-28 Bus controlling system

Publications (1)

Publication Number Publication Date
JPS5790733A true JPS5790733A (en) 1982-06-05

Family

ID=15833288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16654780A Pending JPS5790733A (en) 1980-11-28 1980-11-28 Bus controlling system

Country Status (1)

Country Link
JP (1) JPS5790733A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0130036A2 (en) * 1983-06-28 1985-01-02 Rca Licensing Corporation Interconnection apparatus
JPS6260048A (en) * 1985-09-10 1987-03-16 Nec Corp Bus circuit for data processor
JP2010507304A (en) * 2006-11-03 2010-03-04 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング Apparatus and method for manipulating communication messages

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0130036A2 (en) * 1983-06-28 1985-01-02 Rca Licensing Corporation Interconnection apparatus
JPS6260048A (en) * 1985-09-10 1987-03-16 Nec Corp Bus circuit for data processor
JPH0564367B2 (en) * 1985-09-10 1993-09-14 Nippon Electric Co
JP2010507304A (en) * 2006-11-03 2010-03-04 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング Apparatus and method for manipulating communication messages
US8407388B2 (en) 2006-11-03 2013-03-26 Robert Bosch Gmbh Device and method for manipulating communication messages

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