JPS5671881A - Decoder circuit - Google Patents

Decoder circuit

Info

Publication number
JPS5671881A
JPS5671881A JP14823679A JP14823679A JPS5671881A JP S5671881 A JPS5671881 A JP S5671881A JP 14823679 A JP14823679 A JP 14823679A JP 14823679 A JP14823679 A JP 14823679A JP S5671881 A JPS5671881 A JP S5671881A
Authority
JP
Japan
Prior art keywords
signal
level
gate circuit
delay
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14823679A
Other languages
Japanese (ja)
Inventor
Hiroshi Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14823679A priority Critical patent/JPS5671881A/en
Publication of JPS5671881A publication Critical patent/JPS5671881A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To reduce the delay in the access to the cell memory information, by adding a transistor to the final stage gate circuit and decreasing the delay in the trailling of work line at the transistion of status. CONSTITUTION:A transistor Q30 controlled with a signal -CS' is added to the final stage gate circuit G3, and the circuit G3 constitutes an NOR gate which takes the output N2 of the gate circuit G2 and the signal -CS' as an input. When the signal -CS' is at the standby period in H level, the work line W is made at L level independently of the level of the output H2 of the gate circuit G2. Accordingly, when the period is moved from the decode period to the standby period, without waiting the operation of the gate circuits G1, G2 due to the level change of the address signal inputs A1, -A2', A3..., the word line with selected state, e.g., W1 has faster trailing with the level change of the signal -CS'. Thus, the delay in the access to the cell storage information can be reduced.
JP14823679A 1979-11-15 1979-11-15 Decoder circuit Pending JPS5671881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14823679A JPS5671881A (en) 1979-11-15 1979-11-15 Decoder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14823679A JPS5671881A (en) 1979-11-15 1979-11-15 Decoder circuit

Publications (1)

Publication Number Publication Date
JPS5671881A true JPS5671881A (en) 1981-06-15

Family

ID=15448288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14823679A Pending JPS5671881A (en) 1979-11-15 1979-11-15 Decoder circuit

Country Status (1)

Country Link
JP (1) JPS5671881A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203277A (en) * 1981-06-10 1982-12-13 Nec Corp Address inverter buffer circuit
EP0083195A2 (en) * 1981-12-28 1983-07-06 Fujitsu Limited Decoder circuit for a semiconductor device
JPS5979493A (en) * 1982-10-29 1984-05-08 Hitachi Micro Comput Eng Ltd Eprom device
JPS62205596A (en) * 1986-03-05 1987-09-10 Mitsubishi Electric Corp Input buffer circuit for mos type memory device
JPH03116495A (en) * 1990-06-01 1991-05-17 Hitachi Micro Comput Eng Ltd Eprom device
EP0730278A1 (en) * 1994-08-31 1996-09-04 Oki Electric Industry Company, Limited Semiconductor memory device
US5977799A (en) * 1994-08-31 1999-11-02 Oki Electric Industry Co., Ltd. Decoding circuit for a storing circuit

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203277A (en) * 1981-06-10 1982-12-13 Nec Corp Address inverter buffer circuit
JPS6223395B2 (en) * 1981-06-10 1987-05-22 Nippon Electric Co
EP0083195A2 (en) * 1981-12-28 1983-07-06 Fujitsu Limited Decoder circuit for a semiconductor device
US4563598A (en) * 1981-12-28 1986-01-07 Fujitsu Limited Low power consuming decoder circuit for a semiconductor memory device
JPS5979493A (en) * 1982-10-29 1984-05-08 Hitachi Micro Comput Eng Ltd Eprom device
JPH0136200B2 (en) * 1982-10-29 1989-07-28 Hitachi Maikuro Konpyuuta Enjiniaringu Kk
JPS62205596A (en) * 1986-03-05 1987-09-10 Mitsubishi Electric Corp Input buffer circuit for mos type memory device
JPH03116495A (en) * 1990-06-01 1991-05-17 Hitachi Micro Comput Eng Ltd Eprom device
EP0730278A1 (en) * 1994-08-31 1996-09-04 Oki Electric Industry Company, Limited Semiconductor memory device
US5977799A (en) * 1994-08-31 1999-11-02 Oki Electric Industry Co., Ltd. Decoding circuit for a storing circuit

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