JPS6223395B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS static type circuit, and more particularly to an address inverter buffer circuit whose power consumption is controlled by an external signal and which uses a depletion type MOS transistor as an output transistor.

Conventionally, as this type of address inverter buffer circuit, there is a circuit having a configuration as shown in FIG. MOS transistors Q1 to Q15 constitute an address inverter buffer circuit, where:
MOS transistors Q2, Q5, Q8, Q10,
Q12 is a depression type MOS transistor,
Transistors Q1, Q3, Q4, Q6, Q7, Q
9, Q11, Q13, Q14, and Q15 are enhancement type MOS transistors.

An input address signal applied to terminal A outputs complementary signals of the same polarity and opposite polarity to output terminals A' and A', respectively.

The signal applied to the terminal CB is a signal that has a high potential when selected and a low potential when not selected, and turns off transistors Q1, Q4, and Q7 when not selected.
Cuts the current flowing through Q1, Q4, and Q7.

The signal applied to the terminal is a signal that has a low potential when selected and a high potential when not selected, and resets the levels of nodes 4 and 6 to low potential when not selected. The signals at output terminals A' and ', together with other address signals, are each input to a decoder circuit as shown in FIG. In this type of circuit, the rising characteristic of the decoder circuit output B depends on the falling characteristic of the outputs A' and ' of the address inverter buffer circuit, and faster falling of A' and ' leads to higher speed. However, the above address inverter buffer circuit has the following drawbacks.

In other words, the address inverter buffer circuit output, which was at a low potential in the previous cycle, is in a non-selected state.
Depression type because nodes 4 and 6 are at low potential.
It is at a level that is increased by the threshold voltage of the MOS transistor. However, the output of the address inverter buffer circuit, which was at the power supply _Vcc level in the previous cycle, maintains the power supply level in a floating state even when not selected. Therefore,
When the address input is switched in the next cycle, the output of the address inverter circuit, which is at the power supply level, falls slowly. As a result, there is a drawback that the rise of the decoder output is delayed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address inverter buffer circuit that has improved fall characteristics, prevents the floating state of the output of the address inverter buffer circuit when not selected, and is stable against power supply fluctuations.

The address inverter buffer circuit in the present invention has power consumption controlled by an external selection signal,
And depreciation type MOS is used as output transistor.
A drain and a source terminal are connected between complementary outputs of an address inverter buffer circuit using transistors, a drain terminal is connected to a first transistor having a gate terminal to which a signal is applied when not selected, and the complementary output, The source terminal is connected to a reference voltage source, and is composed of a pair of second and third transistors for guaranteeing the potential of complementary outputs when not selected.

As a result, when the complementary output of the address inverter buffer circuit is not selected, it is set to an intermediate potential between the power supply potential and the ground potential, and the second and third transistors forming a minute current path ultimately displace the complementary output. An address inverter buffer circuit that can be set to a potential increased by the threshold voltage of the type MOS transistor and has an output with good falling characteristics is constructed.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows an address inverter buffer circuit equipped with an address output reset circuit according to the present invention.
MOS transistors Q1 to Q15 constitute the same address inverter buffer circuit as shown in FIG. MOS transistor Q16,
Q17 and Q18 are MOS transistors constituting the output reset circuit of the present invention, transistor Q16 is an enhancement type MOS transistor, and Q17 and Q18 are depletion type MOS transistors. The drain and source terminals of transistor Q16 are connected to address inverter buffer circuit output terminals A','. It is connected to the gate terminal of transistor Q16, and a power supply voltage level is applied when it is not selected. The drain terminals of transistors Q17 and Q18 are connected to address inverter buffer circuit output terminals A' and ', respectively, and the gate and source terminals are connected to a ground voltage source.

In FIG. 3, when the address inverter buffer circuit shifts from selected operation to non-selected operation, that is, when the CS terminal changes from high potential to low potential and the terminal changes from low potential to high potential, transistor Q1 , Q4, and Q7 are turned off, cutting off the current path. Also, transistors Q14 and Q15 are turned on, and nodes 4 and 6 have a low potential.
At this time, the address inverter buffer circuit output, which was at the power supply _Vcc level in the previous cycle, becomes a floating state. The output, which is at a low potential, tries to rise by the threshold voltage of the depresion type MOS transistor. When transistor Q16 turns on at this point, it pulls down the output, which is floating at the power supply level, and also
The output that is at a low potential is pulled up, resulting in the complementary output being at a potential midway between the power supply potential and ground potential.
Transistors Q17 and Q18 are transistors that create a minute current path between the complementary output and ground to prevent the complementary output from floating when the power supply _Vcc fluctuates. When the output is not selected, the potential can be kept at a potential that is increased by the threshold voltage of the depletion type MOS transistor. As a result, since the fall of the output falls below the intermediate level when not selected, the fall time can be made faster.

FIG. 4 shows the output waveform of the address inverter buffer circuit of FIG. 3, where the dotted line waveform shows the corresponding waveform of FIG. B in the same figure is the second
This figure shows the relationship between the decoder output waveforms, and it can be seen that the rise characteristics of the decoder output are improved by adding the output reset circuit of the present invention.

As explained above, in the address inverter buffer circuit of the present invention, the output of the address inverter buffer circuit is not in the floating state of the power supply level when not selected, but is set to an intermediate potential between the power supply potential and the ground potential. Depression type MOS
Because it can be set to a potential that is increased by the threshold voltage of the transistor, the falling characteristics of the address inverter buffer output can be improved in the next cycle.
As a result, it has the excellent feature that the decoder circuit output rises quickly, and also has the excellent feature of being resistant to power supply fluctuations.

[Brief explanation of the drawing]

Figure 1 shows a conventional output transistor in which power consumption is controlled by an external signal and the output transistor is a depreciation type.
FIG. 3 is a diagram showing an address inverter buffer circuit using MOS transistors. 2 is a diagram showing a decoder circuit, FIG. 3 is a diagram showing the same address inverter buffer circuit as in FIG. 1 with an output reset circuit of the present invention, and FIG. 3 is a diagram showing operating waveforms of the address inverter buffer circuit and the decoder circuit of FIG. 2. FIG. Q2, Q5, Q8, Q10, Q12...depression type MOS transistor, Q1, Q3, Q
4, Q6, Q7, Q9, Q11, Q13, Q1
4, Q15...Enhancement type MOS transistor.

Claims (1)

[Claims] 1 The drain and source are connected between the complementary outputs of an address inverter buffer circuit whose power consumption is controlled by an external selection signal and which uses a depletion type MOS transistor as the load transistor in the output section, and a conduction signal is applied when it is not selected. An address inverter buffer circuit comprising a first transistor having a gate terminal, and second and third depletion type MOS transistors having drains connected to respective complementary outputs and having gate and source terminals connected to a reference voltage source.