JPH04160815A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To convert the level of a small amplitude signal at high speed to output the result by providing a prescribed gate bias the same as that of a current source MOS transistor(TR) of a current mirror type differential amplifier circuit to a MOS TR at the load side so as to supply a prescribed load current to the load. CONSTITUTION:When the output of a 1st differential amplifier circuit 10 is at an intermediate level, the output node N2 of a 1st level conversion circuit 12 is set to an H level close to the level of a Vcc. Moreover, when the output of a 2nd differential amplifier circuit 11 is at an intermediate level, the output node N5 of a 2nd level conversion circuit 13 is set to an L level close to the level of a Vss. During this setting, both switching TRs Q12, Q15 in the level conversion circuits 2, 13 are electrified. During that time a gate voltage of output REs Q19, Q20 is set to each threshold voltage or below when an output terminal 4 is kept to a high impedance state. Thus, the output buffer circuit capable of stable and high speed operation against fluctuation in various parameters is realized.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an output buffer circuit used in a semiconductor integrated circuit, and in particular, converts a small amplitude differential signal to a large amplitude level in a semiconductor memory, etc. The present invention relates to an output buffer circuit that converts and outputs the converted data.

(Prior Art) As the chip area of semiconductor memories such as DRAMs increases due to the increase in capacity, wiring delays during transfer of signals read from memory cells to output pins have become a major problem. As a method for reducing the influence of wiring delays and achieving high-speed data transfer, a small-amplitude differential signal system using a differential amplifier circuit is being used instead of the conventional large-amplitude signal transfer system using a CMOS inverter. It has been proposed to configure a data transfer circuit using

By the way, in a memory configured using MOS transistors, compatibility with TTL is generally guaranteed as an input/output level. Therefore, when the data transfer circuit is configured with a small amplitude differential signal system as described above, the output buffer section requires a level conversion circuit that converts the small amplitude differential signal into a large amplitude signal in order to drive the output TTL load. It becomes necessary.

FIG. 9 is an example of such a conventional output buffer circuit.

The minute signals RD and FT5 are received by the current mirror type differential amplifier circuit 100, where they are amplified to a certain amplitude, and the output V. is amplified by the CMOS inverter 101. C
MOS inverters 102 and 103 are buffer stages for increasing current drive capability. Output V of the current mirror type differential amplifier circuit 100. By adjusting the dimensions of each transistor so that D out swings around the circuit threshold of CMOS inverter 100, this circuit can obtain an output signal D out that swings fully up to the power supply voltage.

However, such conventional output buffer circuits have the following problems. As mentioned above, in this conventional circuit, the center of the output amplitude of the current mirror differential amplifier circuit 100 is set to C.
It is necessary to set it near the circuit threshold of MOS inverter 101.

However, since the circuit configurations of the two are different, if there is a change in parameters such as transistor threshold voltage, power supply potential, temperature, etc., the output amplitude center of the current mirror differential amplifier circuit 100 and the circuit threshold of the CMOS inverter 101 A gap occurs between the two.

The input/output signal system is completely asynchronous, and one side is always “
If a differential signal in which one is at "H" level and the other is at "L" level is input, there is not much of a problem.However, if the signal transfer system is a synchronous system like in a normal DRAM, When equalizing the input signal lines and holding them at the same potential for a predetermined period of time, the differential amplifier circuit 10
An output of 0 is an intermediate level. This intermediate level is exactly C
The output of the inverter becomes unstable because it is close to the circuit threshold value of the MOS inverter 101. Furthermore, in this state, a through current flows through the CMOS inverter, which increases power consumption.

(Problems to be Solved by the Invention) As described above, the conventional output buffer circuit has the problems of being unstable with respect to various parameter fluctuations and having a large through current.

The present invention has been made in view of these points, and provides an output buffer circuit that is stable against various parameter fluctuations, has low through-current, and is capable of level-converting and outputting a small-amplitude signal at high speed. The purpose is to

[Structure of the Invention (Means for Solving the Problems) The output buffer circuit according to the present invention is based on a current mirror type differential amplifier circuit and a CMOS-configured level conversion circuit that receives the output thereof. A current mirror type differential amplifier circuit consists of a pair of first conductivity type driver MOS transistors whose sources are commonly connected and whose respective gates serve as differential input terminals, and a second conductivity type driver MOS transistor provided on the drain side of these driver MOS transistors. It is constituted by a current mirror type load consisting of a MOS transistor, and a first conductivity type current source MOS transistor provided on the common source side of the driver MOS transistor and whose gate is given a constant bias.

Although the level conversion circuit has a CMOS configuration, the gates are not common. That is, a second conductivity type driver MOS transistor whose gate receives the output of the differential amplifier circuit;
A level conversion circuit is constituted by a first conductivity type load MO9 transistor to which the same gate bias as that of the current source MO5I transistor of the differential amplifier circuit is applied. This level conversion circuit also includes a driver MOS transistor and a load M.
A switching MOS transistor of the first conductivity type is inserted on the load MOS transistor side between the OS transistors to detect an output level inversion and cut off a current path.

The output of the level conversion circuit is the output M driven by this.
An OS transistor is provided.

(Function) In the output buffer circuit of the present invention, in the CMOS-configured level conversion circuit section, the MOS transistor on the load side is given the same constant gate bias as the current source MOS transistor of the current mirror type differential amplifier circuit, so that the level conversion circuit section has a CMOS configuration. The state is such that load current can flow. Therefore, even if the output of the current mirror type differential amplifier circuit is at an intermediate potential, the output of the level conversion circuit will not become unstable. Further, when the current mirror type differential amplifier circuit outputs a predetermined output and the driver side MOS transistor of the level conversion circuit is turned on, this is detected and the switching MOS transistor is controlled to be off, thereby cutting off the load current. Therefore, no unnecessary through current flows.

(Example) The present invention will be explained in detail below.

FIG. 1 is an equivalent circuit of an output buffer of one embodiment. In the figure, 1 is the power supply terminal (vCC), 2 is the ground terminal (VCC), and 2 is the ground terminal (VCC).
3 is a small amplitude differential signal RD, FT5
' input terminal, 4 is "H level V cc, "
Output signal D ou whose L° level has full amplitude up to Vss
This is the output terminal from which t is obtained. The input terminal 3 is input to two current mirror type CMOS differential amplifier circuits 10 and 11. The first current mirror type CMOS differential amplifier circuit 10 includes PMOS driver transistors Q2, . . . , whose sources are commonly connected. Q3, these driver transistors Q2. A PMOS current source transistor Ql connected between the common source of Q3 and the power supply Vcc, and driver transistors Q2. N provided on the drain side of Q3
MOSl-transistor Q4. It is composed of a current mirror type load consisting of Q5.

PMOS current source current source transistor gate terminal 5 has
A constant bias voltage vap is applied to this transistor Q1 to cause it to operate as a pentode and serve as a current source. Second
The current mirror type CMOS differential amplifier circuit 11 has a first
The current mirror type CMOS differential amplifier circuit 10 has a complementary configuration. That is, the second current mirror type differential amplifier circuit 11 includes NMOS driver transistors Q7. whose sources are commonly connected. Q8, an NMOS current source transistor QB connected between their common source and ground VSS, and a PMOS transistor Q9 provided on the drain side. It is composed of a current mirror type load consisting of QIO. A constant bias voltage VBN is applied to the gate terminal 6 of the NMOS current source transistor Q6 in order to cause the transistor Q6 to operate as a pentode and serve as a current source.

These first. Second current mirror type differential amplifier circuit 10
．． Complementarily configured level conversion circuits 12 and 13 are connected to the output nodes Nl and N4 of 11, respectively. The first level conversion circuit 12 is a first differential amplifier circuit 1
an NMOS transistor Q13 whose gate is connected to the output node N1 of the first differential amplifier circuit 10;
A PMOS load transistor Qll with the same gate bias as the current source transistor Q1, and a PMOS switching transistor Q1 inserted between them.
2. This PMOS switching
The gate of the transistor Q12 is connected to the output node N2 of the first level conversion circuit 12, that is, the NMOS driver.
It is controlled by a signal obtained by inverting the drain output of transistor Q13 by inverter 14. The second level conversion circuit 13 includes a PMOS driver transistor 01 whose gate is connected to the output node N4 of the second differential amplifier circuit 11.
B. Current source transistor Q6 of second differential amplifier circuit 11
It consists of an NMOS load transistor Q14 given the same gate bias as , and an NMOS switching transistor Q15 inserted between them. The gate of this NMOS switching transistor Q15 is connected to the output node N of this second level conversion circuit 13.
5, that is, it is controlled by a signal obtained by inverting the drain output of the PMOS driver transistor Q1B by an inverter 15.

Here, the PMOS current source transistor Ql of the first differential amplifier circuit 10, the NMOS load transistor Qll of the fifth level conversion circuit 12
, the dimensional relationship of the NMOS driver transistor QLI is the current drive capacity 111 of Qll and the current drive capacity 1 of Ql.
The ratio I 11/I l of 1 is the current drive capability I of Ql3
11 and the current drive capacity I5 of Q5: 113/I5
so that it becomes larger, that is, 111/ I 1 > 113/ I 5 .
- Designed to satisfy (1). However, the current drive capabilities I 1 , I 5 , I 11 .
I13 are transistors Ql and Q5, respectively
, Qll, and Ql3 are expressed as drain currents at the same gate bias. N of the second differential amplifier circuit 11
MOS current source transistor QB, PMOS load transistor QIO1, NMOS load transistor Q14 of the second level conversion circuit 13. Similarly, regarding the dimensional relationship of the PMOS driver transistor Q1B, the ratio of the current drive capability 114 of Q14 to the current drive capability I6 of QB is 114/I
6 is larger than the ratio I 1B/I 10 of the current drive capability I 1B of QIB and the current drive capability 110 of QIO, that is, 114/I 6 > 116/I 10 .
- Designed to satisfy (2).

1st. Output node N2. of conversion circuit 12.13 to second level. N5 are the final stage PMOS output transistors Q19 . Connected to the gate of NMOS transistor Q20. These output transistors Q19. Each gate of Q20 has
PMOS reset transistor Q17. controlled by reset signals i, φ. An NMOS reset transistor Q1g is provided. These reset transistors Q17. Qlg is a level conversion circuit 12.
At 13, the switching transistor Q12. After the load current is interrupted by Q15, these switching transistors QI2. This is used to restore Q15 to its original conductive state.

The operation of the output buffer circuit configured in this way is
This will be explained with reference to the timing diagram shown in the figure.

At time to, differential input signal RD,n has not yet arrived, and input terminal 3 is in an equalized state. The level is, for example, Vce/2.

At this time, the first. The output nodes Nl and N4 of the second differential amplifier circuit 10.11 are connected to the respective current source transistors Q1.
．． Q6, and a MOS transistor Q4 that constitutes a current mirror type load. Q5, Q9° becomes an intermediate potential determined by the dimensions of QIO. Here, PMO of the first differential amplifier circuit 10
S current source transistor Qi, NMOS driver transistor Q5, PMOS load transistor Qll of the first level conversion circuit 12, NMOS driver transistor Q
The dimensional relationships of 13 are Ql, Q5, Qll, Q
As described above, the ratio of the current drive capabilities of the transistors 13 and 13 is set so as to satisfy the equation (1). Therefore, when the output of the first differential amplifier circuit 10 is at an intermediate potential, the output node N2 of the first level conversion circuit 12 is set to an "H" level close to Vcc. The second differential amplifier circuit 11 and second level conversion circuit 13 side also include transistors QB, Q14 . Q
Since the dimensions of IO, Ql[i are adjusted to satisfy equation (2), when the output of the second differential amplifier circuit 11 is at an intermediate potential, the output node N5 of the second level conversion circuit 13 is at Vss. It is set to "L" level close to . During this time, switching transistors Q12 and Q15 in the level conversion circuits 12 and 13 are both conductive. During this period, the output transistor Q19. The gate voltage of Q20 is below the respective threshold voltage, so the output terminal 4 is held in a high impedance state.

Next, at time tl, a differential signal RD is applied to input terminal 3.

When fm is input (21 in Fig. 2), signal RD becomes “H”.
'' level, the output node N of the first differential amplifier circuit 1°
1 is raised (22 in FIG. 2). As a result, the potential of the output node N2 of the first level conversion circuit 12 is lowered (23 in FIG. 2), and the PMos output transistor Q19 is turned on, so that the output terminal 4 is set to "H".
"Level output D out is obtained (27 in Figure 2)
. At this time, when the level of the node N2 becomes lower than the threshold voltage of the inverter 14, the output node N2 of the inverter 14
3 becomes "H" level, and the PMOS switching transistor Q12 is turned off. This disconnects the load transistor Qll of the first level conversion circuit 12,
From this point on, no through current flows in the level conversion circuit 12 of node 1. Therefore, the gate of PMOS output transistor Q19 is rapidly discharged by driver transistor Q13, and its potential is lowered (24 in FIG. 2). On the other hand, the output node N4 of the second differential amplifier circuit 11 outputs "H" level in response to the same input (25) in FIG.
This completely turns off the PMOS driver transistor Q16 of the second level conversion circuit 13. Therefore, the output note N5 of the second level conversion circuit 13 is 'L'
level (26 in FIG. 2), and the NMOS output transistor Q20 is held in the off state. This "H level" state of the output D out is maintained even if the input signal returns to the equalized state (29 in FIG. 2).Therefore, by raising the reset signal φR (32 in FIG.
), the potential of node N2 is forcibly raised (3 in Figure 2).
0), returns the switching transistor Q12 of the first level conversion circuit 12 to the conductive state. As a result, even after the reset signal is released (31 in FIG. 2), the high impedance state of the output terminal 4 is maintained.

Even when the input signal RD goes to the "L" level and the "L level" is output from the output terminal 4, the same explanation can be given, except that the circuit operations of the two complementary systems are reversed.

As described above, in the output buffer circuit of this embodiment, even when the inputs of the differential amplifier circuit are equalized, the circuit does not become unstable as in the conventional case.

Furthermore, the through current is effectively suppressed by the action of the switching transistor inserted in the level conversion circuit.

FIG. 3 shows an output buffer circuit according to another embodiment of the present invention. Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. In this example, the first. In order to speed up the output reset of the second differential amplifier circuit 10.11,
Short-circuiting MOS transistors Q30°Q31 are provided which are controlled by control signals φR and 1-. Also number 1. The second level conversion circuits 12.13 have their output nodes N2. A latch circuit 31. to hold the level of N5.
32 are provided. These latch circuits 31.32
is constituted by, for example, a clocked CMOS inverter controlled by a latch signal φL as shown in FIG. As is well known, a clocked CMOS inverter consists of two PMOS transistors Q40. Q4
1 and two NMOS transistors Q42. It is composed of Q43. Furthermore, output transistor Q19.
, Q 20 are provided with control circuits 33 and 34 for controlling their switching. One control circuit 33 includes a PMOS transistor Q32 provided between the gate of the PMOS output transistor Q19 and the power supply terminal Vcc and controlled by a signal φE, a node N2 and a PMOS transistor Q32, which is controlled by a signal φE.
N is connected in parallel between the gates of the MOS output transistor Q19 and controlled by the signal φg+-, respectively.
MOS transistor Q34 and PMOS transistor Q3
5.

The control circuit 34 also includes an NMOS output transistor Q20.
An NMOS transistor Q33 provided between the gate of the node and the ground terminal Vss and controlled by the signal E, and a node N5
An NMOS transistor Q3B and a PMOS transistor Q are connected in parallel between the gate of the output transistor Q3B and the gate of the NMOS output transistor Q20, and are controlled by the signal φ82, respectively.
37.

The basic input/output operation of the output buffer circuit of this embodiment is the same as that of the previous embodiment. However, short circuit transistor Q
30. The characteristics are improved by adding Q31, latch circuits 31, 32, and control circuits 33, 34. This will be explained with reference to FIG.

FIG. 5 shows control signals φ3. in the output buffer circuit of this embodiment. φ1. φ2 and input/output signal RD.

[115, D out , and level conversion circuit 12.
13 output node N2. It shows the relationship of N5. Control signal φE is an enable signal, and when it is at the "H" level, the gates of output transistors Q19, Q20 are connected to transfer gates Q34, .
Q35. Q3B, node N2. N
Connected to 5. When the control signal φ8 is at “L” level, the transistor Q32.033 in the control circuit 33.34
is on, output transistor Q19. The gates of Q20 are connected to V ec and V ss, respectively, to force cutoff, and the output terminal becomes a high impedance state. Therefore, as shown in FIG.
becomes “H” level before the input signal arrives (51)
, an output signal Dout corresponding to the input signal RD, [15] is obtained at the output terminal 4. Control signal φE than signal input
If the rise of N2. is slow (52), the output node of the level conversion circuit N2. After the signal is obtained at N5, the control signal φ2
The output signal D out is obtained only when D out rises.

The latch signal φ, after receiving the input signal RD, ff5,
After a predetermined time has elapsed, it becomes "H° level" and is maintained at "H" level until the next new input signal is input. Therefore, after the input signals RD and RD are equalized (54)
However, by raising the enable control signal φ8 again (53), the latch circuits 31 and 32 cause the node N2
．． The data held in N5 is output. Furthermore, by inputting the latch signal φL, for example, the input signal RD becomes “H”.
When the node N2 becomes 'L' level, this node N2 is discharged not only by the driver transistor Q13 of the first level conversion circuit 12 but also by the transistors Q42 and Q43 in the latch circuit 31. Therefore, as mentioned above, In response to the rise of control signal φ8 after input signal equalization, the gate potential of PMOS output transistor Q19 can be lowered at high speed.The gate potential of NMOS output transistor Q20 can be raised at high speed as well.

Output control using the control signal φE as described above is performed using, for example, D
Column address strobe signal (“
It is essential to realize the general control functions required for

Further, in this embodiment, the first. Second differential amplifier circuit 10.
Short circuit MOS transistor Q3 added to 11 respectively.
0. Q31, their output nodes N2. The reset time of N5 can be shortened. This enables high-speed data switching.

In the output buffer circuits of FIGS. 1 and 3, a through current flows through the differential amplifier circuit section and the level conversion circuit section.
If power consumption becomes a problem, the through-current path may be cut off except during data transfer.

FIG. 6 shows such an embodiment. This shows the configuration of the output pull-down side, that is, the second differential amplifier circuit 11 side, in an embodiment based on the circuit shown in FIG. 1 and added with a circuit element for cutting off the through-current path. As shown in the figure, the driver transistor Q of the differential amplifier circuit 11
7. An NMOS switching transistor Q61 is inserted between the common source of Q8 and current source transistor Q6. In addition, a PMOS switching transistor Q80 is connected between the output node N4 of the differential amplifier circuit 11 and the power supply terminal.
is provided. These switching transistors Q60. The gate of Q81 receives activation control signal φ5.
controlled by

When the activation control signal φS is at the "H° level," the switching transistor Q81 of the differential amplifier circuit 11 is on, and the switching transistor Q60 of the output node N4 of the differential amplifier circuit 11 is off, which is different from the previous embodiment. Data transfer is performed in the same way.The activation control signal φ is set to the "L" level except during data transfer.At this time, since the switching transistor Q60 is off, the through-current path of the differential amplifier circuit 11 is At this time, the switching transistor Q60 is turned on and the output node N4 of the differential amplifier circuit 11 is kept at "H" level, so the PMOS driver transistor 01B of the level conversion circuit 13 is turned off. Therefore, no through current flows in the level conversion circuit 13. At this time, the output node N5 of the level conversion circuit 13 is maintained at the "L" level.

By adding similar circuit elements to the output connector side, unnecessary through current can be eliminated.

In the above, the output stage PMOS transistor Q19
Although a case has been described in which two systems of differential amplifier circuits and level conversion circuits with complementary configurations are provided for the NMOS transistor Q20, the present invention also applies to the case where only one system of differential amplifier circuits and level conversion circuits is provided. It is valid.

FIGS. 7 and 8 are output buffer circuits of such embodiments. The embodiment shown in FIG. 7 uses the pull-down side differential amplifier circuit 11 and level conversion circuit 13 in FIG.
This is an embodiment in which a PMOS output transistor Q19 and an NMOS output transistor Q20 are controlled.

The embodiment shown in FIG. 8 is an embodiment in which the pull-up side differential amplifier circuit 10 and level conversion circuit 12 in FIG. 1 control the PMOS output transistor QI9 and the NMOS output transistor Q20.

The circuits of these embodiments differ from the previous embodiments in that they are two-state buffers, but basically the same effects as in the previous embodiments can be obtained. The circuits of these embodiments are also useful as level conversion circuits that convert differential signals into full amplitude signals. And if it is operated at full amplitude, the subsequent CM
Through current in the O8 circuit can be reduced.

[Effects of the Invention] As described above, according to the present invention, the circuit threshold value of the level conversion circuit section is automatically set to an appropriate value with respect to the amplitude center of the output of the differential amplifier circuit that handles minute input signals. An output buffer circuit that is stable against fluctuations in various parameters and capable of high-speed operation is obtained. Further, by inserting a switching transistor for cutting off load current into the level conversion circuit section, the through current can be effectively reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an output buffer circuit of one embodiment of the present invention, FIG. 2 is a timing diagram for explaining its operation, FIG. 3 is a diagram showing an output buffer circuit of another embodiment, and FIG. 3 is a diagram showing the configuration of the latch circuit used in FIG. 3, FIG. 5 is a timing diagram for explaining the circuit operation of the embodiment of FIG. 3, and FIG. 6 is a diagram showing the outline of the output buffer circuit of another embodiment. FIG. 7 is a diagram showing the output buffer circuit of still another embodiment. FIG. 8 is a diagram showing the output buffer circuit of still another embodiment. FIG. 9 is a diagram showing the conventional output buffer circuit. FIG. 1...Power terminal (Vcc), 2...Ground terminal (V
ss), 3...input terminal, 4...output terminal, 5.
6... Control gate terminal, 10... First current mirror type differential amplifier circuit, 11... Second current mirror type differential amplifier circuit, 12... First level conversion circuit, 1
3... Second level conversion circuit, 14.15... Inverter, Q19... NMOS output transistor, Q2
0...PMOS output transistor, Q12. Q1
5...Switching transistor, Q17. Q1
8...Reset transistor, 31.32...Latch circuit, 33.34...Gate control circuit. Applicant's agent Patent attorney Takehiko Suzue 1st rili Figure 2 Figure 4 Figure Tk 6 Figure ΦR Figure 7

Claims (4)

[Claims] (1) A current mirror consisting of a pair of first conductivity type driver MOS transistors whose sources are commonly connected and whose respective gates serve as differential input terminals, and a second conductivity type MOS transistor provided on the drain side of these driver MOS transistors. a current mirror type differential amplifier circuit configured by a first conductivity type current source MOS transistor provided on the common source side of the driver MOS transistor and whose gate is given a constant bias; A driver MOS transistor of a second conductivity type to which the output of the amplifier circuit is input to the gate and a load MOS transistor of a first conductivity type to which the same gate bias as the current source MOS transistor is applied, and these driver M
a level conversion circuit in which a switching MOS transistor of a first conductivity type is inserted on the load MOS transistor side between an OS transistor and a load MOS transistor to detect an output level inversion and cut off a current path; and an output of the level conversion circuit. Driven output MOS
An output buffer circuit comprising a transistor. (2) A current mirror type load consisting of a pair of PMOS driver transistors whose sources are commonly connected and whose respective gates serve as differential input terminals, an NMOS transistor provided on the drain side of these PMOS driver transistors, and the PMOS A first current mirror type differential amplifier circuit constituted by a PMOS current source transistor provided on the common source side of the driver transistor and whose gate is given a constant bias; A pair of NMOS driver transistors as differential input terminals, these NMOS
P provided on the drain side of the S driver transistor
A current mirror type load consisting of a MOS transistor, and the NMOS driver, which is provided on the common source side of the transistor and whose gate is given a constant bias.
a second current mirror type differential amplifier circuit constituted by a MOS current source transistor; an NMOS driver transistor whose gate receives the output of the first current mirror type differential amplifier circuit; and the PMOS current source transistor. The first transistor has PMOS load transistors to which the same gate bias is applied, and a PMOS switching transistor is inserted on the load transistor side between these driver transistors and load transistors to detect output level reversal and cut off the current path. a level conversion circuit; a PMOS driver transistor whose gate receives the output of the second current mirror differential amplifier circuit; and an NMOS load transistor to which the same gate bias as the NMOS current source transistor is applied; a second level conversion circuit in which an NMOS switching transistor is inserted on the load transistor side between the driver transistor and the load transistor to detect an output level reversal and cut off a current path; and the first level conversion circuit. PM driven by output
an OS output transistor; and an NMOS connected in series with the PMOS output transistor, which is driven by the output of the second level conversion circuit.
An output buffer circuit comprising: an output transistor; (3) The first level conversion circuit is configured such that its output is set to the "H" level when the potentials of the input signal pair of the first current mirror differential amplifier circuit are equal.
The dimensional relationship between the PMOS current source transistor and the NMOS load transistor of the current mirror type differential amplifier circuit, the PMOS load transistor and the NMOS driver transistor of the first level conversion circuit is set, and the second level conversion circuit an NMOS current source transistor of the second current mirror differential amplifier circuit such that the output is set to the "L" level when the potentials of the input signal pair of the second current mirror differential amplifier circuit are equal; PMOS load transistor, NMOS load transistor of the second level conversion circuit and PMOS driver
3. The output buffer circuit according to claim 2, wherein the dimensional relationship of the transistors is set. (4) A PMOS reset transistor for forcibly conducting the turned-off PMOS switching transistor is provided at the gate of the PMOS output transistor, and a PMOS reset transistor is provided at the gate of the NMOS output transistor, and the turned-off NMOS switching 3. The output buffer circuit according to claim 2, further comprising an NMOS reset transistor for forcing the transistor to conduct.