KR940008121Y1 - Circuit highy enabling word-line - Google Patents

Abstract

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Description

Wordline High Speed Enable Circuit

1 is a schematic diagram of a conventional SRAM.

2 is a timing diagram of a read operation in FIG. 1.

3 is an equivalent circuit diagram of a conventional word line.

4 is a word line high speed enable circuit diagram according to the present invention;

* Explanation of symbols for main parts of the drawings

ødec: Decoded clock øSEN: Sense amplifier clock

1: Memory cell 1: Word line

2: address decoder 3: sense amplifier

4, 5: switching gate transistor 6, 6 ': inverter

7, 8: bit line 9: address

R: Resistor C: Capacitor

11-13: Transistor

The present invention relates to a word line high speed enable circuit of a memory, and in particular, it is possible to make stable cell data within a short access time by making word line selection of SRAM faster. A word line high speed enable circuit is provided.

In the related art, as shown in FIG. 1, an address 9 and a decoding clock ødec are applied to an address decoder 2, and the address decoder 2 is a switching gate transistor. The memory set (4,5) and the inverter (6,6 ') are connected to the word line (1), and the bit lines (7,8) of the memory set (Sense Amp) Is connected to the data bus DB. In synchronization with, the selected word line 1 at the falling edge begins to charge from the low level to the high level.

As a result, the switching gate transistors 4 and 5 are turned “on” so that the cell data is loaded on the bit lines Bit and Bits 7 and 8 connected to the selected word line, and the data is transferred to the sense amplifier 3. Level sencing is used to ensure that "high, low" data is loaded on the data bus (DB) and read.

However, in this conventional technical configuration, as shown in FIG. 2, the output of the word line starts to rise at the rising edge a of the decoding clock? DEC at read time, and at this time, the switching gate transistor ( The word line 1 needs to be charged as soon as 4 and 5 can operate during the " t ₃ " period in FIG.

In this case, as shown in FIG. 3, the most severe case is the node b connected to the resistor R and the capacitor C farthest from the output of the address decoder, based on the delay time at the node b. Since the cycle of the read cycle must be determined, the data access time is long.

Accordingly, the configuration of the word line high-speed enable circuit according to the present invention to improve the above disadvantages in detail according to the accompanying drawings as follows.

In FIG. 4, the gate of the transistor 13 is connected to the word line 1 farthest from the output of the address coder 2, and the transistor 12 is connected to the gate of the transistor 12. 13 is connected to the drain of the transistor 11 to which the power supply Vcc is applied, and the source of the transistor 12 is connected to the gate of the transistor 11, and then a decoding clock ødec is applied. The operation state of the above described technical configuration is as follows.

In the decoding clock ødec rising edge a of FIG. 2 of the word line 1 selected in FIG.

At this time, when the level of the node 15 of FIG. 4 becomes "high" to some extent, the transistor 13 is operated so that the gate input level of the transistor 12 is "low" and the transistor 12 is "on". The word line 1, which is the node 15, is rapidly charged to a high level so that cell data can be loaded on the bit line faster.

At this time, if the decoding clock? Dec is at the "low" level, the transistor 11 is operated to "turn off" the transistor 12.

Therefore, the word line high speed enable circuit according to the present invention has the effect of making data access more stable and faster by shortening the enable time of the word line.

Claims (1)

A transistor 13 connected to the word line 1 farthest from the output of the addressed coder 2 and operating when the node 15 level of the word line 1 reaches a predetermined state, and the transistor 13 Is configured to include a transistor 12 which is activated when the operation is performed to accelerate the charging of the node 15 and a transistor 11 which is operated by the decoding clock ødec to drive the transistor 12. High speed enable circuit.