JPH035000B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to memory circuits such as bipolar memory circuits having current-switched memory cells.

A bipolar memory circuit having a current switching type memory cell distinguishes between a read cycle and a write cycle of information by receiving a write control signal.

Therefore, if noise is added to the write control signal during the read cycle period, for example, it will cause malfunction.

In order to prevent the circuit from malfunctioning due to the above noise, the write control signal and a delayed signal are logically synthesized as described in Japanese Patent Application Laid-open No. 52-35535, and the delay time is There are methods to remove pulse noise as follows. However, according to the above-mentioned known method, since the write time is reduced as a result of logic synthesis, the pulse width of the write control signal supplied from the outside must be increased, which increases the write cycle period.

An object of the present invention is to provide a memory circuit that performs a stable write operation at high speed.

Another object of the present invention is to provide a memory circuit that can increase the application timing margin of a write control signal.

Another object of the present invention is to provide a memory circuit in which the reference potential generated by changes in the operating current of the information reading circuit is small.

Further objects of the invention will become apparent from the following description and drawings.

According to the present invention, a pulse generation circuit is provided which forms a signal having a predetermined time delay with respect to a write control signal supplied from the outside and having a constant pulse width regardless of the pulse width. The output signal of the pulse generation circuit is substantially used as a write control signal for the memory cell.

Hereinafter, this invention will be explained in detail along with examples.

FIG. 1 is a block diagram of a bipolar memory circuit showing one embodiment of the present invention.

1 is a memory array, which has multiple current switches (emitter coupling) as will become clear later from Figure 3.
Type memory cells and multiple word lines W ₁₁ to W ₃₂₁
and a plurality of digit lines _D1 to _D64 .

2 is an X address decoder, and by receiving multiple bit address signals _A0 to _A4 ,
One of the plurality of word lines of the memory array 1
Forms an X address selection signal for selecting a book.

A word driver 3 selects the word line by receiving the output of the X address decoder 2.

Reference numeral 4 denotes a Y address decoder which receives address signals _A5 to _A9 of multiple bits to form Y address selection signals _Y1 to _Y32 for selecting a plurality of digit lines in the memory array.

Reference numeral 5 denotes a digit line selection circuit, which selects a plurality of digit lines in the memory array according to the Y address selection signal.

FIG. 3 shows a specific example of the memory array 1, the X address decoder 2, the word driver 3, and the digit line selection circuit 5 shown in FIG.

The memory array 1 includes resistors R ₁ , R ₂ ,
Memory cells MS ₁₁ to MS ₂₂ constituted by diodes D ₁ and D ₂ and multi-emitter transistors Q ₁ and Q ₂ and arranged in a matrix, words commonly connected to a plurality of memory cells arranged in the same row. lines W ₁₁ , W ₂₁ , lower word line W ₁₂ , commonly connected to multiple memory cells arranged in the same row;
W ₂₂ , above lower word line W ₁₂ , W ₂₂ and negative power supply terminal
It consists of holding current limits IR ₁ and IR ₂ connected between V _EE and digit lines D ₁ to D ₄ commonly connected to a plurality of memory cells arranged in the same column.

The X address decoder 2 selects address buffers BA ₀ to BA ₄ that output inverted signals and non-inverted signals for input address signals, and selects the output signals of the address buffers BA ₀ to BA ₄ as the respective bases. Transistor Q ₃ to Q ₄
and a transistor receiving a reference voltage E ₁ at its base
NOR circuit 2 consisting of Q ₅ and resistors R ₃ and R ₄
1' to 25'.

The word driver 3 is composed of emitter follower circuits 31 to 35, each of which includes an emitter follower transistor _Q6 .

The digit line selection circuit 5 includes a write and read circuit 51, a selection circuit 52, and a constant current circuit 53.
It consists of

The write and read circuit 51 includes transistors _Q7 to _Q10 provided corresponding to the digit lines _D1 to _D4 . One of the pair of digit lines D ₁ and D ₂ , D ₃ and D ₄
Transistor Q ₇ with emitters connected to D ₁ and D ₃
and Q ₉ have their collectors commonly connected to the sense line S ₁ ,
The bases are commonly connected to the write line _W1 .
Similarly, transistors Q ₈ and Q ₁₀ connected to the other digit lines D ₂ and D ₄ have their collectors connected to the above sense line.
It is commonly connected to the sense line S ₂ that is paired with S ₁ , and its base is commonly connected to the write line W ₀ that is paired with the write line W ₁ .

The selection circuit 52 selects the digit lines _D1 to
Transistor Q ₁₁ or Q provided corresponding to D ₄
Contains Q ₁₄ . The Y address selection signal of the Y address decoder 5 is connected to the bases of the transistors _Q11 and _Q12 corresponding to the pair of digit lines _D1 and _D2 .
Y ₁ is supplied and similarly the other pair of digit wires
Transistors Q ₁₃ and Q ₁₄ matched to D ₃ and D ₄
A Y address selection signal _Y2 is supplied to the base of the Y address selection signal Y2.

The constant current circuit 53 connects each digit line to
It consists of constant current means _IR3 to _IR6 connected between _D1 to _D4 and the negative power supply terminal _VEE .

Reading and writing of information during selection, non-selection and selection of the memory cells of the memory array 1 is carried out by the transistors of the memory cells commonly connected to the digit line, the transistors of the read/write circuit 51 and the transistors 52 of the selection circuit. Determined according to current switching operation.

That is, the unselected word line is set to a relatively low potential (hereinafter referred to as V _L ), and the selected word line is set to a relatively low potential among the collector potentials of the two transistors Q ₁ and Q ₂ in the memory cell connected to this word line. The lower potential of the two transistors in the memory cell connected to the above unselected word line
A relatively high potential (hereinafter referred to as V _H ) is set so as to be higher than the higher of the collector potentials of Q ₁ and Q ₂ .

The potential of the unselected Y address selection line is the above V _H
The potential of the selected Y address selection line is set to a high potential (hereinafter referred to as V _YH ) that is slightly higher than
A potential (hereinafter referred to as V _YL ) is set lower than the lower collector potential of the two transistors Q ₁ and Q ₂ in the memory cell connected to the selected word line.

During reading, the write lines W ₁ and W ₀ are
It is set to a reference potential (hereinafter referred to as V R) between the collector potential of transistor Q ₁ and the collector potential of transistor Q ₂ of the memory cell connected to the selected word line, and at the time of writing, it is set to a reference potential (hereinafter referred to as V _R ) depending on the information to be written. The selected one is set to a potential lower than the lower potential of the two collector potentials (hereinafter referred to as L _WL ), and the other is set to approximately the reference potential _VR .

For example, if Y address selection line _Y1 is not selected,
The high potential V _YH of the Y address selection line Y ₁ turns on the transistors Q ₁₁ and Q ₁₂ of the selection circuit 52, and the transistors Q ₁₁ and Q ₁₂ are connected to the constant current means and IR ₃ and IR ₄ . Current is supplied from Therefore, emitters l ₁ and l ₃ connected to digit lines D ₁ and D ₂ in memory cells MS ₁₁ and MS ₂₁ remain in the off state. Further, transistors Q ₇ and Q ₈ of the read/write circuit 51 also remain in the off state. In this case, a current for holding information flows through the memory cells MS ₁₁ and MS ₂₁ by the holding current means IR ₁ and IR ₂ .

Memory cell MS ₁₁ is selected by word line W ₁₁ and Y address selection line Y ₁ . In _this case _, the selection circuit 5
The second transistors Q ₁₁ and Q ₁₂ are in the off state.

Although not particularly limited, 1 in the storage information in the memory cell corresponds to the on state of transistor Q ₁ and the off state of transistor Q ₂ , and 0 corresponds to the off state of transistor Q ₁ and the on state of transistor Q ₂ .

If the information of the selected memory cell MS ₁₁ is 1 at the time of reading, the base potential of the transistor Q 1 of this memory cell MS ₁₁ is higher than the base potential VR of the transistor Q 7, and therefore, the base potential of the transistor Q ₁ is higher than the base potential _VR of the transistor Q ₇ . Constant current means from emitter l ₁ of Q ₁
A current is applied to IR ₃ . On the other hand, the base potential of the transistor _Q2 is lower than the base potential _VR of the transistor _Q8 , and a current flows from the transistor _Q8 to the constant current means _IR4 . The above current causes a voltage drop across the load resistor _R6 connected to the sense line _S2 . i.e. selected memory cell MS ₁₁
Sense line S ₁ is set to high level and S ₂ is set to low level in response to the stored information of 1 in .

During writing, for example, the write line _W1 is set to the low potential _VWL , and the _W0 is set to the reference potential _VR .
In this case, regardless of whether the transistor Q ₁ of the memory cell MS ₁₁ is previously on or off, the current switching operation of the transistor Q ₁ and the transistor Q ₇ causes a constant current to flow from the emitter l ₁ of the transistor Q ₁ to the constant current means. A current is applied to IR ₃ . As a result, transistor Q ₁ is turned on and memory cell MS ₁₁
1 will be written as information.

In FIG. 1, _B2 to _B4 are input buffer circuits that receive a chip selection signal, a write control signal, and a data input signal Din, respectively, which are input from the outside.

The buffer circuit _B2 outputs a signal in phase with the input chip selection signal to be supplied to the buffer circuit _B1 and the gate circuits _G1 and _G2 . In this embodiment, as will be clear from the description below, the chip, ie, the memory circuit, is brought into the selected state by the low level of the chip selection signal, and is brought into the non-selected state by the high level of the chip selection signal.

The buffer circuit _B3 outputs a signal in phase with an input write control signal to be supplied to a pulse generation circuit 6, which will be described later, and a signal in opposite phase to be supplied to the buffer circuit _B1 . The write control signal is set to a low level when writing information to the memory cell, and set to a high level when reading information from the memory cell.

The buffer circuit _B4 outputs a signal having the opposite phase to the input data signal Din to be supplied to the gate _G1 , and a signal having the same phase to be supplied to the gate circuit _G2 .

As shown in FIG. 2, the pulse generation circuit 6 includes a first delay circuit 7 that delays the write control signal supplied from the buffer circuit _B3 , and a delay signal outputted from this delay circuit 7 and the write control signal supplied from the buffer circuit B3. NOR gate circuit with control signal as input
_G3 , a second delay circuit 8 that delays the output signal of this gate circuit _G3 , and a reset circuit that uses the output of the gate circuit _G3 as a set input and the output of the second delay circuit 8 as a reset input. and a priority flip-flop circuit 9, from the inverted output of the flip-flop circuit 9 to the gate circuit.
This is to obtain the write control signal ′ input to G ₁ and G ₂ .

Gate circuit _G1 has an input buffer as described above.
By receiving the chip selection signal via _B2 , the write control signal' via the pulse generation circuit 6, and the inverted signal of the input data signal Din via the buffer circuit _B4 , a write signal is applied to the write line _W1. Output. The write signal on the write line _W1 is applied to the reference potential when the write control signal' supplied from the pulse generation circuit 6 is at a high level and when the input data signal Din is at a low level corresponding to the information 0. V _R , and when the write control signal ' is at a low level and the input data signal Din is at a high level corresponding to the information 1, the low potential V _WL is set.

The gate circuit G ₂ has the same configuration as the gate circuit G ₁ described above except that it receives a signal similar to the input data signal Din via the buffer circuit B ₄ , and therefore the write control signal ′ is at a low level. And only when the input data signal Din is at a low level corresponding to the information 0, a signal at the level of the low potential V _WL is output to the write line _W0 , and at other times, a signal at the level of the intermediate potential V _R is output. .

Each circuit block having the above configuration is formed on one semiconductor substrate using well-known semiconductor integrated circuit technology.

FIG. 5 shows a time chart of the bipolar memory circuit having the above configuration.

The chip is placed in the selected state in response to the chip selection signal being brought to a low level at time t0.

Next, at time _t1 , address signal Ai is set to a state corresponding to the memory cell to be selected. Time t ₂ after the delay time in the circuit from the above time t ₁
A signal D _OUT corresponding to the information of the memory cell selected in is output.

When writing data, for example, the input data Din is set at time _t3 , and then the write control signal is changed from a predetermined high level to a low level at time t4.

NOR gate circuit G ₃ in pulse generation circuit 6
When the period during which the write control signal is at a low level reaches the delay time _Z1 of the delay circuit 7, a low level signal is received at its two input terminals. That is, the above NOR gate circuit _G9 is
At time _t5 , when time _Z1 has elapsed from time _t4 , a signal that changes from a low level to a high level is output. The RS flip-flop circuit 9 operates at the above time t ₅
is set by the output signal of the NOR gate circuit _G3 at , causing the write control signal ' at its inverted output terminal to go low.

The delay circuit 8 calculates the delay time Z ₂ from the above time t ₅
A signal that becomes high level is output at time t ₆ after . As a result, the RS flip-flop circuit 9 is reset, causing the write control signal ' at its inverting output terminal to go high again.

Therefore, if the low-level period of the write control signal is longer than the delay time _Z1 of the delay circuit 7, the gate circuits _G1 and _G2 always receive a time delayed by the time _Z1 from the write control signal supplied from the outside. The write operation will be performed only for a certain period of time _Z2 .

At time _t7 after the above write operation is completed, the address signal Ai is changed to select a new memory cell, and then the information read or write operation is performed in the same manner as above.

In a bipolar circuit having a current-switching memory cell as described above, the minimum time t _W required to write information to an arbitrary memory cell, that is, the minimum pulse width of the write control signal ', is determined by the sixth As shown by the characteristic curve A in the figure, the write control signal's set-up time t _WSA with respect to the address signal Ai changes. Therefore, the low level period of the write control signal ′, that is, the constant write time Z ₂ is equal to the write time t _W
It is necessary to set it larger than .

According to this embodiment, the low level period Z ₂ of the write control signal' supplied to the gate circuits G ₁ and G ₂
is fixedly determined by the delay circuit 8 in the pulse generating circuit 6, and is not affected by the period of the external write control signal if it is longer than the delay time _Z1 of the delay circuit 7.

Write control signal supplied externally as above
The low level period of WE is not limited by the write time _tW , and can be shortened to the period necessary for starting the pulse generating circuit 6, that is, a period slightly exceeding the delay time _Z1 . In addition, since the write control signal ' is formed internally as described above, the write control signal supplied from the outside uses its backlog a as the address signal Ai.
can be delayed until the backlog of Therefore, the above externally supplied write control signal
WE can increase its timing margin.

The maximum pulse width of the write control signal that is set under the condition that no information is written to any memory cell in the memory array, that is, the Not Write pulse.
As shown by curve B in FIG. 6, the width tnwp varies depending on the setup time t _WSA of the write signal relative to the address signal, and becomes minimum at a predetermined setup time t. The fact that the not write pulse width is small as at the setup time t above means that if pulse noise exceeding the logic threshold voltage is added to the write control signal line, this pulse noise is considered to be the write control signal. This means that information is written to the memory cell by mistake.

According to this embodiment, since the pulse generation circuit 6 is configured to be activated only by a signal having a pulse width of a predetermined time period _Z1 or more, the write control signal supplied from the outside may contain pulse noise. However, this pulse noise is ignored by the pulse generating circuit 6. That is, gate circuit G ₁ ,
By not adding external noise to G ₂ ,
No erroneous write operations occur.

In contrast to this embodiment, if the write control signal supplied from the outside is directly supplied to the gate circuits _G1 and _G2 via the buffer circuit _B3 , the not write pulse width tnwp must be greater than a predetermined value. In order to obtain the address signal, the setup time _tWSA of the write control signal must be greater than a predetermined value.

On the other hand, according to this embodiment, the internally generated write control signal' is delayed by the delay time _Z1 of the pulse generation circuit 6 with respect to the externally supplied write control signal. It is possible to reduce the time difference from the back-wage a of the signal Ai to the back-wage b of the external write control signal to zero. As a result, the timing margin of the external write control signal can be increased.

In this embodiment, the write cycle can be made faster for the reasons mentioned above and for the reasons mentioned above.

Further, as in the embodiment, the operation of the output buffer circuit _B1 is controlled by the write control signal, and the operation timing of the output buffer circuit _B1 is different from the operation timing of the gate circuits _G1 and _G2 . When the configuration is configured such that the following effects can be obtained.

That is, when the output buffer circuit B ₁ has a relatively heavy termination resistor R _L as shown in FIG. 4, the operating current that produces a high level output and the operating current that produces a low level output are different. It will be very different. For example, the operating current that produces a high level output is a large value of about 22 mA,
The operating current that produces the low level output is a small value of about 6 mA.

According to the configuration shown in Figure 1, when there is no write operation, the address signal is output from the output buffer circuit _B1 .
A signal corresponding to the storage information of the memory cell selected by Ai is output. The output of the output buffer circuit _B1 is forced to a low level when a write operation is performed by the low level of the write control signal.

Therefore, for example, as shown in FIG. 5D, when the write control signal is set to low level at time t10, the output buffer circuit _B1 changes its output from high level to low level at time t11, which is approximately the same as time t10. As a result, the operating current will change significantly.

Inductance and resistance components (not shown) of the power supply line of the memory circuit, such as the ground wiring GND
A voltage is generated in response to a large change in the operating current. Therefore, the potential of the ground wiring GND changes as shown in FIG. 5I.

In this embodiment, the write operation is performed by the delay circuit 7 in response to an external write control signal.
The timing of the fluctuation of _the power supply line and the front edge of the write pulses W ₀ and W ₁ (write operation start timing) are
It is possible to shift the phase with the Therefore, a write operation can be performed in a stable power supply voltage state.

In FIG. 7, the write control signal output from the buffer circuit B ₃ is supplied to the output buffer circuit B ₁ via the integrating circuit 10 in order to reduce potential fluctuations in the power supply line.

As a result, the rate of change in the rise and fall of the control signal of the buffer circuit _B1 can be reduced, so the voltage fluctuation of the power supply line GND can be reduced.
Even if this fluctuation timing and the rising timing of write pulse W ₁ are synchronized,
This makes it possible to perform stable write operations.

In addition, the control signal WE of the above output buffer circuit _B1
is the input buffer circuit _B3 that forms this signal WE
The rate of change in the rise or fall may be reduced by, for example, reducing the output drive capability of the output voltage.

The present invention is not limited to the embodiments described above, and the pulse generating circuit 6 can be modified in various ways, and depending on the logic level, a NAND gate circuit or the like may be used as the gate circuit _G3 . Further, the flip-flop circuit 9 and the delay circuit 8 may be replaced with a one-shot multivibrator.

The pulse generating circuit 6 includes a resistor as shown in FIG.
The write control signal may be supplied from a logic circuit comprising R ₇ to R ₉ , transistors Q ₂₀ to Q ₂₃ , and reference voltage sources E ₂ and E ₃ and receiving the chip selection signal and the write control signal. .

In FIG. 8, during the read operation, the bases of the transistors _Q25 and _Q26 are set at a higher potential than the reference potential _E4 , so they are turned on. In response to this, transistors Q ₂₇ and Q ₂₈ are turned off. Out of the transistors Q ₂₉ and Q ₃₀ , the current of the transistor turned on by the input data signal Din is passed through the transistor Q ₂₅ or Q ₂₆ to the resistor R ₁₀ , so that the write lines W ₁ ,
The potential of W ₀ is set to the same potential of _VR .

During write operation, the above transistor
Q ₂₅ and Q ₂₆ are turned off. At this time, for example, if the input data signal Din is at a high level, the transistor _Q29 is on and the transistor _Q30 is off.
The current of the transistor Q ₂₉ above is the current of the transistor Q ₂₈
The write line _W1 is brought to _{the low potential V WL ,} and _the write _{line W0} is brought to the intermediate potential _VR .

Note that a control signal for the output buffer circuit is output from the line l connected to the resistor _R7 .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a logic circuit diagram of a pulse generation circuit according to the present invention, FIG. 3 is a specific circuit diagram of a memory array, and FIG. is a specific circuit diagram of the output buffer circuit, FIG. 5 is an operating waveform diagram of the bipolar memory circuit according to the present invention, FIG. 6 is a write characteristic curve diagram of the bipolar memory circuit, and FIG. 7 is a diagram of the write characteristic curve of the bipolar memory circuit according to the present invention. FIG. 8 is a main logic circuit diagram showing another embodiment. FIG. 8 is a circuit diagram of another embodiment. DESCRIPTION OF SYMBOLS 1...Memory array, 2...X address decoder, 3...Word driver, 4...Y address decoder, 5...Digit line selection circuit, 6...Pulse generation circuit, 7, 8...Delay circuit, 9 ...Flip-flop circuit, 10...Integrator circuit, B ₁ ...
Output buffer circuit, _B2 to _B4 ...Input buffer circuit, _G1 to _G3 ...Gate circuit.

Claims (1)

[Claims] 1. An input gate circuit that transmits input data from the outside to a memory array, an output buffer circuit that transmits stored data from the memory array to the outside,
and a delay means for delaying a write control signal inputted from the outside, the input gate circuit receiving the write control signal at its input via the delay means, and the output buffer circuit receiving the write control signal via the delay means. The input gate circuit receives the write control signal at its input without any interference, and the operation timing of the input gate circuit in response to the write control signal input from the outside is delayed from the operation timing of the output buffer circuit. A memory circuit featuring: