JP2754603B2 - Memory data output circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory data output circuit, and more particularly to a memory data output circuit constituted by MOS field effect transistors.

[Conventional technology]

Conventionally, a row address and a column (C) are stored in a semiconductor memory.
olumn) In the dynamic random access memory using the multi-address method that takes in the address in a time-division manner, the access from the switching of the column address is set by making the column system static. There are a fast page mode and a static column mode in which a column address can be read at a high speed for a predetermined row address.

FIG. 3 is a data output circuit diagram of a conventional dynamic random access memory having such a function.

As shown in FIG. 3, NO4 to NO5 are NOR circuits, and NA6 and NA7 are
NAND circuit, I7, I8 inverting circuit, Q _N5 to Q _N6 are N-channel MOS
Type field effect (hereinafter referred to as MOSFET), N _{15 to} N ₂₀ are nodes,
OE is an output enable signal generated internally by an external signal ▲ ▼ (column address strobe), DRST
The data output circuit reset signal, DO / ▲ ▼ is internally amplified output data, and DOUT is its external output data.

FIG. 4 is a signal waveform diagram for explaining the operation of the output circuit shown in FIG.

As shown in FIG. 4, when the external signal ▼ (row address strobe) goes from high level to low level, the address taken in at that time becomes the selected row address, and then the column address for the row address is changed. The address is ready to be fetched. FIG. 4 is a time chart from this state. Here, when ▼ changes from the high level to the low level, OE changes from the low level to the high level. By this, depending on the state of the nodes N ₁₅ and N ₁₈ at that time, N
_17, the state of the N ₂₀ is determined. In the first page mode, when ▲ ▼ changes from high level to low level, the column address at that time is latched.
If the address is changed before ▼ falls, the change is sensed by the ATD (address transfer director) circuit provided inside and a one-shot signal from low level to high level is generated, and DO / ▲ ▼ at that time Nodes N ₁₅ and N ₁₈ are both low,
, The nodes N ₁₇ and N ₂₀ are both set to the low level to turn off both the transistors Q _N5 and Q _N6 .
That is, the data output circuit is reset once. This DR
Since DO / ▲ ▼ is settled during one SHOT of ST, if OE is at a high level, when DRST goes to a low level, DOUT is output according to DO / ▲ ▼ at that time. That, DO is high, ▲ ▼ is if low, N ₁₇ turns from low level to high level, DOUT is high level is output. Further, DO / ▲ ▼ is N ₂₀ turns from low level to high level, if the reverse, DOUT low level is outputted. At this time, when the output data changes from high level to low level or from low level to high level when OE is high level first, both transistors _QN5 and _QN6 It is for turning on and preventing the output of correct data from being delayed. In addition, if the DOUT terminal is connected to the power supply and the GND via a resistor, respectively, the output is returned to Hi-Z once and output, so that apparent access can be seen quickly. However, if the DOUT terminal is simply provided with a capacitor or the like, DOUT does not return to the Hi-Z (intermediate potential) state even when both the transistors Q _N5 and Q _N6 are turned off. Becomes high enough soon, the data of the previous address remains output. This is the waveform of DOUT shown in FIG.

In the static column mode, only the address is not latched by ▲ ▼, and there is no change in other basic operations.

[Problems to be solved by the invention]

In the memory DATA output circuit described above, access from address switching is set when the column system is static, but if the DOUT unit is connected only to the capacitance, Since the output data is held, when the output data changes from a high level to a low level or from a low level to a high level by switching the address, the above-described conventional data output circuit outputs the data. Changes from the high level to the low level or from the low level to the high level, so that there is a drawback that the output is slower than when outputting from the Hi-Z (intermediate potential) state to the high level or the low level.

It is an object of the present invention to provide a memory data output circuit that enables high-speed access when outputting such data.

[Means for solving the problem]

According to the memory data output circuit of the present invention, a data output reset signal and a column generated in one shot in response to an address switch for output data generated internally.
A memory data output circuit that controls a voltage of an output terminal connected to a connection point of the plurality of output transistors by controlling a plurality of output transistors connected in series by combining an output enable signal based on an address strobe signal. , Connected to the output terminal,
An NOR circuit, a NAND circuit and an internal circuit formed of transistors for a plurality of intermediate potentials connected in series, and when the column system is in a statically operable state, the data output reset signal is used to output the plurality of outputs. In addition to turning off both transistors, the internal circuit directly returns output data to the intermediate potential once using the data output reset signal, and then outputs correct data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an output circuit diagram of memory data for explaining an embodiment of the present invention.

As shown in FIG. 1, NO1 to NO3 are NOR circuits, and NA1 to NA5
NAND circuit, I ₁ ~I ₆ inverting circuit, Q _N1 to Q _N4 is N-channel MOSFET, and the output enable signal N ₁ to N ₁₄ is a node, OE is to be internally generated by the external signal ▲ ▼, DRST data output The reset signal, DO / ▲ ▼ represents output data amplified internally, and DOUT represents its external output data.

Next, the operation of the memory data output circuit will be described with reference to the time chart of FIG.

As shown in FIG. 2, ADD represents an external address.
In the same manner as in the conventional example described above, ▼ is a time chart from when the column level is first changed from the high level to the low level and the column system is statically operable. When ▲ ▼ changes from a high level to a low level, OE changes from a low level to a high level, and data output is enabled. If the address is changed before that, the ATD circuit changes the low to high level 1
DOT signal of SHOT is output. Here, while OE and DRST are both high, nodes N ₃ and N ₆ are both low, that is, Q _N1 and Q _N
Both _N2 are turned off. At this time, like the conventional example,
If only the capacitance is connected to the DOUT pin,
While holding the state of the previous cycle or previous address and OE and DRST are both at a high level, in this case N ₇ is the ratio circuit or DOUT respect NO3, NA4 is DOUT potential for low-level if potential than the intermediate potential N ₁₁ becomes the low level. Thus, the transistor Q _N4 and ON N ₁₄ becomes the high level, the potential of DOUT from the high level to the low level. Conversely, if DRST is at a low level, since N ₈ goes high, the transistor Q _N3 becomes N ₁₀ is the high level is turned ON. Therefore, since the potential of DOUT is to be changed from the low level to the high level, the output of DOUT becomes the intermediate potential regardless of the high level or the low level. Next, if PRST goes from high to low while OE remains high, N ₇ goes high and N
_10, N ₁₄ both become low level, the transistor Q _N3, Q _N4 are both turned off. On the other hand, since the correct DO / ▲ ▼ is settled while DRST is high, if DRST goes low, DO at that time is high, and if ▲ ▼ is low, N ₃ goes from low. transistor Q _N1 becomes high level is turned on, DOUT is made from the intermediate potential to the high level.
Conversely, if DO is low and ▲ ▼ is high, N
₁₆ goes from a low level to a high level, and DOUT goes from an intermediate potential to a low level. Therefore, if the data of the previous cycle or the previous address is at a high level and the data is at a low level, the output of DOUT is returned to the intermediate potential once by using an internal circuit and then the original data is output. Access becomes possible.

〔The invention's effect〕

As described above, the memory data output circuit of the present invention can operate in any state of the circuit external to the DOUT terminal, regardless of whether the output data in the previous cycle or previous address is high or low. Returning the output of DOUT to the intermediate potential state once and then outputting the original data, that is, taking the intermediate level without a large amplitude change from high level to low level or low level to high level, There is an effect that can be accessed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a memory data output circuit for explaining an embodiment of the present invention, FIG. 2 is a signal waveform diagram of the memory data output circuit shown in FIG. 1, and FIG. FIG. 4 is a signal waveform diagram in the output circuit shown in FIG. NO1~NO5 ...... NOR circuit, NA1~NA7 ...... NAND circuit, I ₁ ~I ₈
…… Inverting circuit, Q _{N1 to} Q _N6 …… N-channel MOSFET, N ₁ to
N ₂₀ … node, OE …… Output enable signal, DRST …… Data output circuit reset signal, DO / ▲ ▼ …………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… ateded

Claims (1)

(57) [Claims] A plurality of serially connected output data generated internally in combination with a data output reset signal generated in one shot for address switching and an output enable signal based on a column address strobe signal. In a memory data output circuit that controls a voltage of an output terminal connected to a connection point of the plurality of output transistors by controlling the output transistor, the memory data output circuit is connected to the output terminal, and a NOR circuit, a NAND circuit, and a series connection Having an internal circuit formed of transistors for a plurality of intermediate potentials, when the column system is in a statically operable state, using the data output reset signal, and turning off the plurality of output transistors together, Output data directly in the internal circuit using the data output reset signal A memory data output circuit for outputting correct data after returning to an intermediate potential once.