JPS59181828A - Output buffer circuit of semiconductor element - Google Patents

Abstract

PURPOSE:To attain high speed by bringing an output to an intermediate level between 0 level and 1 level prior to the change in an input signal so as to reduce the access time in an output buffer circuit. CONSTITUTION:The 1st transistor (TR)MOS1 conducting its output to a power supply VDD and the 2nd TRMOS2 conducting its output to ground VSS are provided in parallel with an output buffer TR comprising a load TRQ1 and a drive TRQ2. A transition detector circuit TD detects the change in an address input signal so as to give a detecting signal having a prescribed pulse width to a control circuit CS, the MOS1 and MOS2 are turned both on and the output is brought into the intermediate level. Since the level is set to the intermediate level unit the change in an output potential atteded with the change in an address signal is transmitted to the output buffer, the operation is quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an output buffer circuit for semiconductor devices such as semiconductor memories and microprocessors that require high speed performance.

[Technical background of the invention and its problems]

Conventionally, an output buffer circuit of a semiconductor device that handles digital signals such as a semiconductor memory or a microprocessor has a load transistor Q1 that drives a load on the output OUT side to a "1" level and a transistor with a pin level of 0#, as shown in FIG. By controlling the dart of each transistor Q1 + Q2, a drive transistor Q2 is set up to drive the
1" or "o" is read.

However, in such an output buffer circuit,
Since a large load capacitance CL is driven, the output waveform changes slowly. In this case, if the load transistor Qt+drive transistor Q2 has sufficient driving ability, the output signal can be made to follow the change in the input signal in a short time. However, unnecessarily increasing the driving capacity of the output buffer stage is not desirable for purposes of reducing power consumption and power.

For this reason, for example, in the case of semiconductor memory, the so-called access time, which is the time required for the address signal to change to select a desired memory cell and its contents to be output, becomes long, which hinders speeding up. There was a problem with being exposed.

FIG. 2 is a time chart showing how an address signal changes in a semiconductor memory, an arbitrary memory cell is selected, and the stored contents are outputted to the outside as data output. In other words, FIG. 2 (a) is an address signal, and (b) is a data signal, and when the data output changes from a 0" reading state to a 1" reading state, and from a 1" reading state to an "o" reading state. If you do so, there will be a delay and the access time will be longer.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and allows the output signal to follow changes in the input signal in a short time.
It is an object of the present invention to provide an output buffer circuit for a semiconductor device that can shorten access time and increase speed.

[Summary of the invention]

That is, the present invention sets the output to 0 before the input signal changes.
” level and “1” level f
t'l? It is a sign.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the block diagram shown in FIG. 3, with reference to an example in which the present invention is applied to a semiconductor memory.

In FIG. 3, Ql and Q2 are a load transistor and a drive transistor, respectively. A first transistor M is connected in parallel to the output buffer transistor consisting of the load transistor Q1 and the drive transistor Q2 to conduct the output to the power supply vDD.
O81, a second transistor MO82 is provided to conduct the output to ground vss. Then, the TD detects a change in the address input signal A using a transition detector circuit, and provides a detection signal with a predetermined pulse width to the control circuit C8. Then, the output of the control circuit C8 causes the first. Second
The transistors MO81 and MOS2fi are made conductive at the same time, and the output potential is set to an intermediate potential between the 1" level and the 0" level. That is, the first and second transistors M
O8I.

When the MOS 2 id 7 dress input signal changes, they are both conductive for a predetermined period and the output potential is changed to each transistor MO8.
1. The potential is set to be an intermediate potential between the 1" level and the "o' level, which is determined according to the ratio of the on-resistance values of MOS 2. Therefore, the first. Each second transistor MO8l, MOS
If the on-resistance values of 2 are R1 and 'Ft2, respectively, the output level potential VOUT is given by the following equation.

Nao, tube 1 during this period. second transistor MO81,
Since both MOS 2 become conductive, a current path is created from the power supply 'VDD to the ground VSS. Therefore, in order to reduce power consumption, first. second transistor MO8
1. The current gain, or transconductance, of MOS 2 must be made smaller compared to that of the output buffer transistor. And the first. When the transconductance of the second transistor MO8J and MOS2 is made small, the change in the output potential from the 1'' or '0# level to the intermediate potential will be slow, but the change in the output potential to the intermediate potential will be slower. This can be done before the change in the output potential due to the change in the address signal is transmitted to the output buffer, so there is sufficient time.

Therefore, as shown in FIG. 4(a), in response to a change in the address input signal, the data signal once changes from the "0" level to the intermediate potential M, and then "1" as shown in FIG. 4(b).
'' level, or once changes from the ``1'' level to the intermediate potential M, and then changes to the ``0'' level. Therefore, the access time t can be significantly shortened compared to the conventional output buffer circuit shown in FIG. 1, and the operation speed can be increased.

Note that in order to set the output potential to an intermediate potential between the 'r''1'' level and the Pa0'' level, the first and second transistors M
If one of the output buffer transistors Ql and Q2 becomes conductive while O81 and MOS 2 are turned on, charging and discharging will occur through these transistors, preventing the transition to the intermediate potential. become. In such a case, for example, as shown in the block diagram shown in FIG.
．． While the second transistors MO81 and MOS2 are turned on and the output potential is shifted to the intermediate potential, the input signals to the output sofa transistors Ql and Q2 may be cut off to forcibly maintain the non-conducting state. In other words, in Fig. 5, the output of the transition detector circuit TD is connected directly to one input of NOR1.
It is applied to one input of the gate NOR2 via the inverter NV1. Also the above NOR goo) NORJ,
A data signal read from a memory cell (not shown) is commonly applied to the other input of N0R2. And each NOR above
The outputs of gates NOR1 and NOR2 are connected to inverters INV and ?, respectively. , INV3' to the output buffer transistors Ql and Q2. In this way, the transition detector circuit T
The output buffer transistors Q1 and Qz' can be kept non-conductive while the output from D is applied. Therefore, it is possible to reliably prevent the abrasive wheel from becoming conductive and interfering with potential transition.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to significantly shorten the time required for an output signal to change in response to a change in an input signal, thereby providing an output buffer circuit for a semiconductor device suitable for high-speed operation. .

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional output buffer circuit, Fig. 2 is a waveform diagram explaining the operation of the output/4 buffer circuit shown in Fig. 1, and Fig. 3 shows an embodiment of the present invention. FIG. 4 is a waveform diagram explaining the operation of the output buffer circuit shown in FIG. 3, and FIG. 5 is a block diagram showing another embodiment of the present invention. Ql, Q2...output buffer transistor, cL
...Load capacity, MOS 1, MOS 2...1st. Second transistor, TD...transition detector circuit, C8...control circuit. -14'

Claims (1)

[Claims] (1) Before a change in the input signal is transmitted to the output side,
An output buffer circuit for a semiconductor device, characterized in that the potential on the output side is an intermediate potential between a power supply potential and a ground potential. (2. In the item described in claim 1, each dart of the output buffer is controlled by a load transistor inserted between the output and the power source and a drive transistor inserted between the output and the ground potential. and selectively conduct one of the output buffer transistors, and before the signal applied to the gate of the output buffer changes, the first and second transistors connected in parallel to each of the output buffer transistors are simultaneously rendered conductive and output. An output buffer circuit for a semiconductor device, characterized in that the potential on the side is set to an intermediate potential between the source voltage and the ground potential. (3) In the output buffer circuit according to claim 2, An output buffer circuit for a semiconductor device characterized in that the current gain of the first and second transistors is smaller than that of the first transistor.
．． An output buffer circuit for a semiconductor device, characterized in that the output buffer transistor is forcibly rendered non-conductive during a period in which the second transistor is conductive.