JPH0789437B2 - Semiconductor memory device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a dynamic semiconductor memory having a dynamic memory cell using an insulated gate transistor and a storage capacitor as a memory cell, and a peripheral circuit including a bipolar transistor. The present invention relates to a device, and more particularly to a method of generating an in-chip control signal for performing a normal operation of a dynamic memory device.

[Background of the Invention]

In a semiconductor memory device, in order to realize high speed and high integration at the same time, a memory cell is configured by an insulated gate field effect transistor (hereinafter referred to as MIS transistor), and a peripheral circuit for transmitting / receiving a signal to / from the memory cell. JP-A-55-129994 and JP-A-56-58193 disclose a structure including a bipolar transistor. In these inventions, a flip-flop composed of four MIS transistors and two load elements is used in the memory cell, which is a so-called static memory device. Therefore, there is a drawback that the occupied area of the memory cell is relatively large and it is difficult to achieve high integration. On the other hand, a dynamic type memory for storing "1" and "0" information depending on the presence / absence of charge in the storage capacitor by using one to three MIS transistors and the storage capacitor as shown in FIGS. 55 and 56. The cell is advantageous for high integration because the area occupied by the memory cell is small. However, in the semiconductor memory device using this dynamic type memory cell, it is necessary to rewrite after amplifying the read signal to the data line D because the memory cell does not have the ability of self-reproducing the stored information.
Further, it is necessary to precharge the potential of the data line D to a constant potential before reading. Therefore, the actual dynamic type memory device requires considerably more complicated control than the static type memory device in order to perform the memory operation (reading, writing, information retention). This operation is described in detail in "VLSI Device Handbook" PP291 to PP305 (published by Science Forum Co., Ltd.). However, in the conventional dynamic type memory device including those described here, since both the memory cell and the peripheral circuit are configured by using the MIS transistors, the integration time is high but the speed including the access time is slow. It was

[Object of the Invention]

It is an object of the present invention to provide a semiconductor memory device that can read dynamic memory at high speed.

[Outline of Invention]

The present invention will be described with reference to FIGS. 2 and 4. A dynamic memory cell 2 for storing information and a word line W ₀ for accessing the dynamic memory cell 2 are described.
A data line D ₀ for transmitting information stored in the dynamic memory cell 2 and a data line D ₀ connected to the data line D ₀ ,
The information read from the dynamic memory cells 2 and rewrite amplifier SA1 for rewriting to the dynamic memory cells, connected to the data lines D _0, the dynamic memory cell 2 is read to the data lines D ₀ A read preamplifier SA2 for sensing the above information, a common write data line I connected to the data line D ₀ , and write data from the common write data line I to the data line D _0. A write switch Q ₄₀ and a read common data line 0 connected to the output of the read preamplifier SA2,
The read preamplifier SA2 has its gate connected to the data line, wherein the MOS transistor Q ₂₁ to which the drain or source connected to the read common data lines 0, the magnitude of current flowing through the source-drain path of the MOS transistor The write switch Q ₄₀ includes a MOS transistor Q ₄₀ whose source / drain path is connected between the write common data line I and the data line D _0. At the time of inputting a selection signal for selecting the line W ₀ and a selection signal for activating the read preamplifier SA2 at substantially the same timing, when reading information to the read common data line 0,
The read preamplifier SA2 is the rewrite amplifier SA1.
It is characterized in that it is activated earlier.

Example of Invention

Embodiment 1 FIG. 1 is a block diagram of a dynamic semiconductor memory cell, showing a peripheral circuit group including an N-bit memory cell array 6 and a bipolar transistor. In the memory cell array 6, i word lines W and j data lines D are cross-arranged, and N memory cells C are arranged at the intersections of the word lines and the data lines. Address inputs X _{0 to} X _n and Y _{0 to} Y _m are input to the address buffer circuits 5X and 5Y, respectively.
Is applied to the output of the decoder driver circuit 8X, 8
Transmitted to Y. Of the decoder / driver circuits 8X and 8Y
8X for word line 8Y for write / read circuit 7
Are driven to write information to or read information from the selected memory cell C in the memory cell array 6. Reference numeral 9 denotes a write / read control circuit, which uses a chip select signal ▲ ▼, a write operation control signal ▲ ▼, and an input signal DI for the decoder / driver circuits 8X, 8Y, write / read circuit 7, and output circuit 10. To control. The output circuit 10 is a circuit for outputting the information read by the write / read circuit 7 to the outside. The writing / reading circuit 7 has a decoder
The control signal from the decoder / driver circuit 8Y can be controlled through the memory cell array 6 by arranging it at the end of the memory cell array 6 opposite to the driver circuit 8Y.
In FIG. 1, X system address inputs X _{0 to} X _n , and Y
Although the system address inputs Y _{0 to} Y _m are input from separate input terminals, a method of sharing these input terminals and providing a time difference, that is, a so-called “address multiplex method” can also be adopted. . Also, in the following explanation,
Unless otherwise specified, the external interface is at the level of an emitter coupling logic (hereinafter referred to as ECL), but the present invention is a transistor transistor logic (hereinafter TT).
Write L. ) Can also be applied to.

In ECL, the power supply voltage is V _EE (−5.2V), and TTL
Then, it is V _CC (+ 5V).

FIG. 2 shows in more detail only the memory cell array 6 and the portion 11 of the read / write circuit (7 in FIG. 1) of the sense system circuit for reading and rewriting. FIG. 3 is a waveform showing the operation from reading to rewriting. The circuit for writing data in 7 of FIG. 1 will be described later. In FIG. 2, the sense circuit 11 is composed of a sub-sense circuit 11S provided for each pair of data lines D in the memory cell array 6. In the sub-sense circuit 11S, HP is a precharge circuit, SA1 is a first differential amplifier, and SA2 is a second differential amplifier. The output of the sub-sense circuit 11S is transmitted to the output circuit 10 including a bipolar transistor through the output line O, which is grounded through the resistors R ₃ and R ₄ . N in the first differential amplifier SA1
The channel MIS transistors Q ₁₇ and Q ₁₉ are called sense amplifiers in the conventional MIS dynamic semiconductor memory.
The P-channel MIS transistors Q ₁₆ and Q ₁₈ are called active restore circuits, but since these are a kind of amplifier, they are generically called the first differential amplifier SA1 here. Next, the operation of reading these circuits will be described with reference to FIGS. 2 and 3. Before starting the read operation, set the first differential amplifier SA1 to φ _SA1 , ▲ at the trailing edge of the previous cycle.
Use ▼ to turn off, set the precharge signal φ _P to a high potential, and turn on the precharge circuit HP. As a result, the data line pairs such as D ₀ , ▲ ▼ or D ₁ , ▲ ▼ are short-circuited and the potential is set to the precharge voltage V _H. V _H is set to a value about half the negative power supply voltage V _EE . When the chip select input signal ▲ ▼ becomes low potential, the precharge signal φ _P falls and the precharge circuit H
P is turned off, and the word line W ₀ selected by the address signals X _{0 to} X _n and Y _{0 to} Y _m and the Y selection signal φ _Y0 are transited to the high potential. The MIS transistors of all the memory cells 2 (FIG. 2) connected to the word line W ₀ become conductive, and the data line pair D ₀ , ▲ ▼ or D ₁ , depending on the charge of the storage capacitor CS.
A slight potential difference occurs in ▲ ▼ and so on. This potential difference is
The differential amplifier SA2 detects the output and sends its output O, to the output circuit. The output circuit amplifies this and generates a predetermined output level as DO. In parallel with these operations, φ _SA1 , ▲
The drive circuits 15 and 16 controlled by ▼ turn on the first differential amplifier SA1 via the H line and the L line.

By this operation of SA1, the minute differential signal of the data line pair read from the memory cell is amplified, the data line on the high potential side is changed to 0V, the data line on the low potential side is changed to V _EE , and the data line is changed. Rewriting is performed on the memory cell selected by the word line for each pair.

The above is the read operation (including the rewrite operation). Next, the write operation will be described with reference to FIGS. 4 and 5. Fourth
The write circuit 12 shown in the figure constitutes the read / write circuit 7 shown in FIG. 1 together with the sense circuit 11 shown in FIG. The write circuit includes first and second input lines I, MIS transistors Q _{40 to} Q ₄₃ connected in series between these and the data lines D ₁ and ▲ ▼, and gate control lines φ _RW , φ _Y1 and. In the case of writing, as shown in FIG. 5, the operation is exactly the same as the reading operation until the word line is selected from the precharge state and a minute differential signal is generated on the data line pair in which W _{1 is set} to a high potential. At this time, one of the write input lines I, is set to a high potential (0 V) and the other is set to a low potential (V _EE ). Then, the write pulse φ _RW is applied, and the data line pair selected by φ _Y1 is forcibly changed to a potential substantially equal to the potential of I ,. In this way, desired information is written only in the selected memory cell (intersection cell of W ₁ and φ _Y1 ).

The above is a control method for generating a signal group (φ _P , φ _SA1 , ▲ ▼, W, φ _RW ) necessary for driving a memory cell as shown in FIGS. 2 to 5, especially a dynamic semiconductor memory. It does not mention the control method of the data line precharge and its circuit, which are unique to the. Further, there is no mention of the relationship between consecutive operation cycles, and it relates only to the operation of a certain infinite cycle time as shown in FIGS. 3 and 5.

Embodiment 2 FIG. 6 shows operation waveforms of a memory cell drive signal and a memory output signal during a read operation of the dynamic semiconductor memory shown in FIG. In FIG. 3, one infinitely long operation cycle is described. However, in actuality, as shown in FIG. 6, there is a period during which the input becomes low potential and high potential within the finite operation cycle time t _C , and during the period when ▲ ▼ is high potential, the next operation cycle To prepare for this, precharge operation of the data line is performed. That is, the selected word line (W ₀ ) is lowered to deselect all words, the first differential amplifier SA1 is turned off by φ _SA1 , ▲ ▼, and the precharge circuit is operated by φ _P to change the precharge of the data line. To do. These W ₀ , φ _P , φ _SA1 and ▲ ▼ must be switched in a fixed order as the ▲ ▼ input is switched to a high potential as shown in FIG. Also, in FIG. 6, the memory output DO is shown at an intermediate level during the precharge period, but in the ECL interface, it is actually fixed at a low potential, T
The TL interface is often in a high-impedance state, and the output circuit must be controlled so as to match them.

Hereinafter, a method of generating these control signals will be described in detail with reference to embodiments.

First, a method of generating the word line signal W ₀ as shown in FIG. 6 will be described. That is, while the external input signal ▲ ▼ is at a high potential, all the words are deselected in order to maintain the precharge state, and when ▲ ▼ is at a low potential, the address signals X _{0 to} X _{n are selected.}
Thus, only a predetermined word line is selected and brought to a high potential. In this state, reading and rewriting of the memory cell are performed. When the input becomes high potential at the trailing edge of the operation cycle, all words are deselected and precharge operation is performed in preparation for the next cycle. In this way, a function to deselect all words according to ▲ ▼ input (reset function) and a function to fix selection / non-selection of word lines until the rewriting is completed after the word line is selected (latch function) Need to be incorporated. First, an example in which such a function is incorporated in a decoder circuit will be described with reference to FIGS. FIG. 7 shows the word line decoding in multiple stages (8X11 and 8X14 in FIG.
Stage) AND gate circuit. here
5X is an address buffer circuit, 8X1 is a decoder circuit, 8X2 is a word driver circuit, and 8X1 and 8X2 constitute the decoder / driver circuit 8X of FIG. φ _R is a reset signal for deselecting all word lines, and φ _L is a latch signal for fixing the selected state of the word lines. These φ _R ,
φ _L is generated from ▲ ▼ input as described later. FIG. 8 is an operation waveform diagram of FIG. Of the four inputs of the first stage decoder circuit 8X11, three of the address buffer outputs V _A are at high potential, and a high potential signal as shown in the figure is applied to φ _R ,
The output V ₁ has a low potential and the 8 × 12 output V ₃ has a high potential. Here, if φ _L is a high potential, the potential of V ₃ is held by the latch circuit formed by 8X12 and 8X13. Next, φ _R is a low potential,
While φ _L is at a high potential, the potential of V ₃ is fixed without accepting a change in the address input signal. While both φ _R and φ _L are at a low potential, all word lines are unselected regardless of V _A. The data line is precharged while all word lines are not selected. ADR (X _{0 to} X _n ) in the next operation cycle
Input is changed, if any of three inputs V _A of 8X11 becomes low potential, phi _R, is phi _L also filed the same as the previous cycle, seventh
The line W shown is no longer selected and another word line is selected. During standby, the ▲ ▼ input is always set to a high potential, and all the word lines are not selected and the data line is precharged. Also, starting from the timing charts of FIGS. 6 and 8,
In all the timing diagrams described later, the ADR input and ▲ ▼ input are shown in phase, but when the ▲ ▼ input goes to a low potential faster than the ADR input changes, the word line determined by the ADR input in the previous cycle is selected. there is a possibility. Conversely ▲
▼ If the input change is delayed, the memory access time will be ▲
▼ Increases due to the delay in input change. Usually ▲ ▼
Switch the input in phase with the ADR input, or use it with a slight delay. In this case, since φ _R and φ _L are generated from the ▲ ▼ input, the memory access time is determined by the time from the switching of the ▲ ▼ input until the memory output DO is obtained. Next, the influence on the access time due to the addition of the word line reset function and the latch function to the decoder circuit will be described. Normally, 8x11 of the decoder circuits shown in FIG.
Is arranged on the outer periphery of the chip and 8X14 is arranged directly on the periphery of the memory cell array, so that the wiring between 8X11 and 8X12 is long and the wiring capacity is large. Therefore, as the driver circuit 8X12, it is advantageous to use a combined driver circuit of a bipolar and MIS transistor combination type having a large load driving capability, rather than using only a MIS transistor. In FIG. 7, since the driver circuit 8X12 with a gate function is used instead of this driver circuit, the number of logic stages from the ADR input to the word line does not increase. Also, the delay time from when the input becomes low potential to when φ _R becomes high potential can be made substantially equal to the delay time from the change of the ADR input (X _{0 to} X _n ) to the change of V _A. Therefore, the increase in the delay time due to the incorporation of the reset function and the latch function is slight. 8X11 and 8X12 in FIG. 7 can be constructed by using the existing CMOS circuit, bipolar, MIS transistor composite gate and driver circuit as shown in FIGS. 9 and 10, respectively. The word driver circuit can be driven at high speed and with low noise by driving a word line in parallel with a bipolar and a MIS transistor in a composite driver circuit as shown in FIG. 11 which is one embodiment of the prior application A, for example. Here, V _P may be a GND potential or a positive potential may be supplied to apply word boost.

On the other hand, the internal control signals φ _R and φ _L shown in FIG. 8 can be generated as shown in FIG. 13 by using a simple logic circuit as shown in FIG. Next, FIG. 14 shows a second embodiment in which a decoder circuit is provided with a word line signal reset function and a latch function. This is different from Fig. 7 in that the first stage 8X15 of the decoder circuit is a logical sum type gate circuit.
The construction method of 8X16 and 8X17 is the same as in FIG. Where φ _R , φ _L
The pulse waveform of must be different from that of FIG. 15th
The figure shows the operating waveforms of the circuit in FIG. Of the 5 inputs of the first stage decoder, only when all three address buffer outputs V _A are low potential and φ _R and φ _L are low potential, 8X15 output V ₁ becomes low potential and word line W is selected. Make a transition. When φ _L becomes high potential, regardless of φ _R or V _A , V will pass through 8X15
₁ becomes a high potential, and the latch circuit composed of 8 × 16 and 8 × 17 fixes V ₃ to a high potential (selected) or low potential (non-selected) state. When φ _R is at a high potential and φ _L is at a low potential, all word lines are deselected, which corresponds to the data line precharge operation. The 5-input OR shown in 8X15 in FIG. 14 can be relatively easily constructed by using the wired OR connection of the emitter follower circuit using the bipolar transistor. FIG. 16 is a circuit diagram more specifically showing the logical configuration of FIG. This diagram shows an input buffer and decoder circuit for selecting one word out of 512 words by using ECL compatible address input signals X _{0 to} X _8.
Address buffer circuit 5X and gate circuit to generate MOS level signal (about 5V amplitude) from input (0.8V amplitude)
The 8X16 uses a'level conversion circuit '. The input amplitude of 0.8V is amplified to 2.8V at 5X and further amplified to 5V at 8X16. The LS in the address buffer circuit 5X is a level shift circuit. The output V ₁ of 5X is connected in a wired OR manner for every three circuits X ₀ , X ₁ , and X ₂ , and only one of the eight output lines is in the low potential selection state. Both φ _R and φ _L are input to the base of the emitter follower, and φ _L is a CMOS 2-input N
Input to AND gate circuit 8X17. Signal amplitude _{V 2, V 3, V 3} ' is a MOS level signal of approximately 4 V to 5 V. Figure 17 shows φ _R and φ _L
Is a circuit for generating. Fig. 18 shows the signal levels and timings in Fig. 16 and Fig. 17 ▲ ▼ If φ _R is quickly lowered in response to the change of input to low potential, the reset function and latch function will not increase the access time. rare.

The above is the embodiment in which the reset function of the word line signal and the latch function are incorporated in the decoder circuit. Next, the reset function of the word line (all word non-selection function) is incorporated in the word driver circuit including the bipolar transistor. Examples will be given. FIG. 19 is a logic diagram showing that the two word driver circuits 8X21 and 8X22 use the output V _B of the X decoder 8X18 as a common input, and the reset signal φ is supplied to each driver circuit.
Input _x0 and φ _x1 . FIG. 20 is a timing chart of the signal. _Whether or not there are φ _x0 and φ _x1 pulses is determined by the X ₀ input,
The phase and width are determined from the ▲ ▼ input. Only when the X decoder output V _B is at a low potential and φ _x0 and φ _x1 are at a low potential, the corresponding word line is set to the high potential selected state. φ _x0 , φ
_When all of _x1 are at high potential, all word lines are at low potential of non-selection regardless of the address signal (reflected in V _B ), and it is possible to cope with the data line precharge period. In FIG. 19, the output V _B of the X decoder circuit is commonly used for the two word driver circuits 8X21 and 8X22, but the output of one decoder circuit is limited to one driver circuit as shown in FIGS. 7 and 14. Of course, it can be used. On the contrary, it is also possible to use the output of one decoder circuit commonly to three or more driver circuits as described later.

FIGS. 21 and 22 show the logic circuit of the word driver shown in FIG. 19 which is constructed by a concrete bipolar and MIS transistor composite gate driver circuit. In FIG. 21, the word lines are driven by two bipolar transistors, one above the other connected in cascade, so that the load capacitance can be charged and discharged at high speed. On the other hand, in FIG. 22, the lower bipolar transistor is omitted and N
The channel MIS transistor is responsible for discharging the load capacitance, and the bipolar transistor only charges the load capacitance.
With this configuration, it is not necessary to isolate the bipolar transistor for each word. This is because the collector potential of the upper bipolar transistor is 0V in all words, so that it can be formed on the common N-type buried layer (collector). Therefore, the area occupied by the word driver circuit can be reduced. Since the size of an ordinary dynamic type memory cell is very small, it is not easy to arrange the bipolar / MIS transistor composite type driver circuit or decoder circuit in the same repeating pitch as the memory cell. Therefore
In FIGS. 21 and 22, the X decoder circuit is commonly used for two words. Figure 23 extends this method further. In the figure, four X decoder circuits and word driver circuits are arranged in a row in parallel with the word lines for each of the four word lines W ₀ , W ₁ , W ₂ and W ₃ . Further, by using two of the three inputs of the decoder circuit in common to the four decoder circuits, it is possible to prevent an increase in size in the direction perpendicular to the word line. When two inputs from the decoder output V ₃ of the previous stage have a high potential and any one of φ _{x0 to} φ _x3 has a high potential, V _B has a low potential and W _{0 to} W
Either of ₃ becomes the high potential selection state. During precharge or standby, all of φ _x0 to φ _x3 are set to low potential. In this embodiment, both the X decoder and the word driver circuit are arranged so that four words are arranged in parallel with the word lines, but the number of word lines is not limited to four, and any integer can be taken as necessary. Further, in FIG. 24, the X decoder circuit is commonly used as in FIGS.
Individual word driver circuits are arranged in one column in parallel with the word lines. In this embodiment, when three inputs from V ₃ are at high potential and any of φ _{x0 to} φ _x3 is at low potential, any of W _{0 to} W ₃ is selected to be at high potential.

In Fig. 19 to Fig. 24 above, the all-word non-selection function can be incorporated by controlling φ _x0 to φ _x3 . In addition to this function, the word line selection is performed from the memory cell read until the rewrite is completed. It is necessary to incorporate a latch function for fixing the non-selected state into the decoder circuit or address buffer circuit in the preceding stage of the word driver circuit. An embodiment in which the latch function is incorporated in the decoder circuit has already been shown in FIGS. 7, 14 and 16. Next, FIGS. 25 to 27 show an embodiment in which the latch function is incorporated in the input buffer circuit. FIG. 25 shows an address buffer circuit with a latch function using a bipolar transistor, which is suitable for ECL input. In this circuit, when the latch signal φ _L has a higher potential than the reference voltage V _BB2 , the address input X is compared with the reference voltage V _BB1 and the signal level is converted to obtain the buffer output x. When φ _L becomes lower than V _BB2 , the output x, the feedback of the x is effective, and the output x corresponding to the previous address is held. Fig. 25 shows a latch circuit suitable for ECL input, but a minor modification can configure a latch circuit suitable for TTL input. FIG. 26 shows a circuit in which a level shift circuit 31 is added to the input section of the circuit shown in FIG. The operating principle of the latch circuit is exactly the same as in Fig. 25. By combining the latch circuits shown in FIGS. 25 and 26 and the high-amplitude conversion circuit shown in FIG. 17, it is possible to drive a CMOS decoder circuit or the like in the subsequent stage. Figure 27 shows a latch circuit that is also suitable for TTL input, but it uses a CMOS circuit, bipolar, and MIS transistor composite circuit to make the steady-state current zero. A two-stage CMOS circuit provided in the input section converts the TTL input into a high-amplitude MOS level signal. Although the number of stages is two in the figure, the number of stages may be determined in consideration of the through current and the speed. When φ _L is at a high potential, the address input X takes out the buffer output x, via the transfer MOS Q51, flip-flop 32, bipolar and MIS transistor composite driver circuit 33. φ
_{When L} becomes low potential, the transfer MOS Q51 is turned off, the flip-flop 32 holds the previous address, and the corresponding output x, is taken out.

The latch circuit drive signal φ _L can be easily generated by a bipolar or HIS transistor as shown in FIG. 28, or a circuit combining these. Fig. 29 shows Fig. 25, Fig.
Figure 28 shows the operation waveforms. In the period be input noise, such as a broken line in X is phi _L as shown in FIG. 29 is a low voltage output x,
Does not affect.

Next, a description will be given of an embodiment in which an address buffer circuit has a function (reset function) of deselecting all the words during the data line precharge. FIG. 30 is an embodiment showing its logical configuration. Where 5X is the address buffer circuit, 8X1
Is a decoder circuit, and 8X2 is a word driver circuit. Here, a logical sum function is added in the address buffer circuit.
▼ When φ _R created from the input is at high potential, all the words are set to non-selected low potential as shown in Fig. 31, and ▲ ▼
When the input becomes low potential, logical processing is performed so that only a certain word is selected by the address input. FIG. 32 shows an example in which the logic configuration of FIG. 30 is used as a concrete circuit. In this figure, the word line reset function is given to the address buffer circuit, and the latch function is provided in the decoder circuit as in FIG.

Here, by using the current control circuit, between the power supply circuits A and B and the constant current source of the input buffer circuit or the emitter follower circuit.
Switches for the HIS transistors Q ₁ , Q ₂ , Q ₁ ′ and Q ₂ ′ are provided. ▲ ▼ When input is high potential, φ _R is high potential, _R is low potential, Q1, Q ₁ ′ are off, Q _2. , Q ₂ ′ are on and input buffer circuit and emitter follower circuit current is zero. . Then, all outputs of the address input buffer circuit become high potential, and all word lines become non-selected low potential. ▲ ▼
When the input becomes a low potential, φ _R becomes a low potential and _R becomes a high potential, and the voltages V _CSA and V _CSB of the power supply circuits A and B are applied to the constant current source via Q ₁ and Q ₁ ′ to generate a predetermined current. Shed. As a result, only a predetermined word line is selected by the address input. The latch circuit provided in the X decoder circuit is the same as that shown in FIG.

As described above, in this embodiment, it is possible to simultaneously deselect all the word lines during standby or during data line precharge, and to cut off the power consumption of the address buffer circuit and the emitter follower circuit at the same time. Power consumption can be significantly reduced. FIG. 33 shows that the low current source drive voltage φ _R is changed in a pulsed manner for the same purpose. Here, LS, LS2, and LS3 are all level shift circuits. Such a current control method is disclosed in JP-B-53-3.
219 "Pulse Current Source". That is, when the input is at a high potential, φ _R is set at a low potential, and the constant current source of the input buffer circuit or the emitter follower circuit is turned off. ▲ ▼ When the input becomes low potential, φ _R becomes high potential and a predetermined current flows. This circuit can also achieve non-selection of all word lines and power reduction at the same time.

Further, in the control of the word line described so far, a dummy cell is provided separately from the memory cell, and in the method of reading the differential signal of the both to the data line pair, the dummy word line for the dummy cell also has
Although it is necessary to provide the reset function and the latch function like the original word line, the timing can be controlled at exactly the same timing as the word line described above. Also, the storage capacity C of the dummy cell
_SD is set to a fraction of the storage capacity C _S of the memory cell,
The storage voltage of the dummy cell is set to a low potential in advance during precharge. A precharge circuit drive signal φ _P may be used as the drive signal.

The embodiment shown in FIGS. 7 to 33, which has been described so far, has a reset function for deselecting all the word lines corresponding to the data line precharge and selection of the word line during reading and rewriting of the dynamic cell. The latch function for fixing the non-selected state is provided in a part of the circuit from the address buffer circuit to the driver circuit. These functions are necessary only for the word system circuit of the dynamic type memory, and the switching of the column selection signal φ _Y (FIG. 2) does not necessarily have to be synchronized with the switching of the word lines. Therefore, the Y system address buffer circuit 5Y and the decoder driver circuit 8Y are
▼ without control by the input address input Y _o to Y _m
Φ _Y may be switched as it is by the change of. In this way, so-called static column or page mode operation, in which the column selection is switched while the word line is selected, can be freely performed. These operations are described in detail in Baba, Mochizuki, Miyasaka, "Static column type 64K bit dynamic RAM that can easily speed up memory system", Nikkei Electronics, pp.153-pp.175, 9 (1983).
FIG. 34 is Y-system address signal Y _o to Y internal control signal in the case of considering also the switching of _m phi _R, the word line signal W _0, W _1, column select signal φ _Y0, φ _Y1, φ _Y2 and memory output The operation waveform of DO is shown. Cycle # 1 is a cycle in which the word line W ₀ is selected under the control of the input ▼ described so far, and at the same time, the selection transition of φ _Y0 by the input switching of Y _{0 to} Y _m is also shown. The first half of the cycle # 2 is the same as the cycle # 1, but in the latter half of the period, the ▲ ▼ input is not set to a high potential and the word line W
_{With 1} still selected, the next cycle # 3 starts.

At this time, the Y _{0 to} Y _m inputs are switched, and the column selection shifts from φ _Y1 to φ _Y2 . At the end of cycle # 3, the ▲ ▼ input is set to a high potential to shift to the precharge state. Thus, in the three cycles # 1, # 2, and # 3, the selected cell is switched, so that the DO output also changes accordingly. However, the beginning and end of cycle # 1,
In the initial stage of # 2 and # 3, all words are unselected in the final precharge state, so DO is uncertain even if φ _Y is confirmed.
Although this uncertain output is represented by an intermediate potential in FIG. 34, it is often set to a low potential in ECL and a high impedance in TTL, as will be described later. In that case, it is necessary to devise the output circuit as described later.

Now, as shown in FIGS. 2 and 6, the word line signal W, the precharge circuit drive signal φ _P , the drive signal φ of the sense amplifier / active restore circuit (first differential amplifier SA1 in FIG. 2). It is necessary to synchronize with _SA1 and ▲ ▼, and the front-back relation is shown in Fig. 6.

Next, connect such multiple signal groups to one external input signal ▲
FIG. 35 shows an embodiment of a logic circuit controlled and generated by ▼. This figure shows φ _R , shown in Fig. 14 or 16.
In parallel with generating the word line signal W using φ _L ,
The principle circuit form for generating the data line precharge signal φ _P , the drive signal φ _{SA1 for the} sense amplifier and the active restore circuit, and ▲ ▼ is shown. FIG. 36 shows operating waveforms obtained by the circuit of FIG. Before a certain word line W is selected, φ _P is set to a low potential in order to cancel the precharge. After the word line is selected and reading of the memory set starts, φ _SA1 and ▲ ▼ are operated to activate the sense amplifier and the active restore circuit. When the reading and rewriting of the memory cell are completed, the word line is lowered, then φ _SA1 and ▲ ▼ are activated to turn off the sense amplifier and the active restore circuit. After that, φ _{P is set} to a high potential and the data line is set to the precharged state to prepare for the next operation cycle. W and φ _P , φ _SA1 , ▲
Any value can be set for the phase difference of ▼ in consideration of the operating margin around the memory cell. As shown in Fig. 35, appropriate delay circuits (Delay1, Delay2, Delay3, Delay4)
It can be generated freely using a NOR circuit and a NAND circuit.

The above is a method of controlling the drive signals W, φ _P , φ _SA1 , ▲ ▼ of the memory cell for read, the sense amplifier, the active restore circuit, and the data line precharge circuit with one external input signal ▲ ▼ including the timing. showed that.
Next, a method for writing will be shown. Prior application B shown in FIG.
FIG. 37 shows an embodiment of a method of generating the input line signal I and the write gate signal φ _RW in the write circuit of FIG. The other drive signals is a _{W, φ P, φ SA1,} ▲ ▼ showed already the same as the readout. As shown in FIG. 37, I, is a signal and its inverted signal through the buffer circuit of the write data input signal DI. In write cycle ▲
▼ Input becomes low potential, and write input signal ▲
When ▼ becomes low potential, the information specified by the ▲ ▼ input is written in the selected memory cell. φ _RW is ▲ ▼
Φ _{RW is set} to high potential when both input and ▲ ▼ input are low potential. The timing at which φ _{RW is set} to a high potential is preferably set to rise after a certain time has passed since the word line W was set to a high potential. That is, a minute signal appears from the memory cell on the data line immediately after W rises. If writing is performed to the selected data line in this state, the noise induced on the unselected data line from the selected data line may disturb the minute signal of the unselected data line and cause a malfunction. Therefore φ
_RW should be applied after the sense amplifier and the active restore circuit operate and all the data line pair differential signals are sufficiently amplified. Therefore, as shown in FIG. 37, Delay 7 of the delay circuit is used to generate φ _RW with a constant delay time from the input. φ _1NH is an output circuit control signal for controlling the memory output to a constant potential during standby or writing, and the role of this signal will be described later. The timing relationship between the signals of FIG. 37 is shown in FIG. In the figure, φ _RW is applied after φ _SA1 and ▲ ▼ are amplified after the switching data line signal is amplified, and the selected data line is forcibly inverted according to I, and writing is performed to the selected memory cell. In this figure, the trailing edge of φ _RW is ▲ ▼
Although it is determined from the rising edge of the input, depending on the application, it is also possible to generate φ _RW with a constant pulse width inside the chip regardless of the input pulse width.

Or the read time or at the time of writing _{W, φ P, φ SA1,} ▲
▼, φ _RW, etc. External input ▲ ▼, ▲ ▼ Input method is shown. The ▲ ▼ and ▲ ▼ inputs are often used not only for signals around memory cells but also for controlling memory outputs. Φ _1NH already described in FIG. 37 is the memory output control signal, and when waiting or writing,
Clamp the memory output to a constant potential or bring it to high impedance. Read information from the selected memory cell is output only during operation and only during read. For example normal ECL
In a compatible memory, the output during standby or writing is often clamped to a low potential. Also normal TTL
A compatible memory uses a trans-state output method, and the output is often set to high impedance during standby or writing.

An example of a memory output circuit that realizes the above functions by using a bipolar transistor and a MIS transistor is shown in FIGS. 39 to 41 for the ELL output circuit and 42nd for the TTL output circuit.
Figures and 43. FIG. 39 is an ECL output circuit using only bipolar transistors, and FIG. 40 is an operation waveform diagram thereof. During standby or precharge, the output clamp signal φ _1NH is made higher than the reference voltage V _BB to cause the current I _CS to flow from Q ₉ , and the DO output is set to a low potential (-1.7V). ▲
▼ φ _1NH is made lower than V _BB after a certain period of time after the input is switched to the low potential, that is, after waiting for the read signal from the memory cell to appear at the sense output O ,. The current I _CS flows through Q _8, and the DO output becomes high potential (-0.9V) or low potential (-1.7V) depending on the sense output O. FIG. 41 shows an output circuit using both bipolar and MIS transistors. This circuit is ISSCC′82 pp.248 to pp.249 “An ECL Compat
MIS transistors Q ₁₂ and Q ₁₄ for output clamp are added to the output circuit disclosed in "ible 4K CMOS RAM".
Standby or data lines Purichiyaji is phi _{1N H} when becomes a high potential, the Q ₁₄ is turned on, the bipolar transistor Q
Let the base potential of _{15 be} the V _EE potential. Q ₁₅ is turned off,
The DO output becomes a low potential (-2V) equal to the termination potential V _T by the termination resistor R _T outside the chip. When φ 1 _NH is at low potential,
Depending on the sense output O, the DO output becomes high potential (-0.9V) or low potential (-2V). In this way, in this circuit, the low potential of the DO output appears at the termination potential V _T outside the chip via the termination resistance R _T. As described above, in any of the circuits shown in FIGS. 39 and 41, even when the output of the sense circuit is indefinite during standby or during data line precharge, the intermediate potential is prevented from appearing at the DO output and fixed at a low potential.

Figures 42 and 43 show TTL interface bipolar and MIS.
It is a circuit diagram of a transistor composite type output circuit and an example of timing control. During standby (▲ ▼ input; high potential), _φ1NH is _set to low potential. At this time, bipolar for output, MIS
The transistors are on the upper side (Q ₁₁ , Q ₁₂ ) and the lower side (Q ₁₃ ,
Q ₁₄ ), both are turned off and D
O output becomes high impedance. During operation ▲ ▼
After a certain time after the input is switched to the low potential, that is, after the normal memory cell read signal appears from the sense circuit, φ _1NH is _set to the high potential and DO is switched according to the read signal O from the memory cell. It is possible.
When Q ₁₁ and Q ₁₂ are on and Q ₁₃ and Q ₁₄ are off, DO is at high potential (V _CC
-0.7V, information "1"), and conversely Q ₁₁ and Q ₁₂ are off, Q ₁₃ and Q
_{When 14} is on, DO becomes low potential (0V, information “O”).

Now, in order to operate the aforementioned sense amplifier and active restore circuit (SA1 in FIG. 2), these drive signals φ _SA1 ,
Apply ▲ ▼ to the circuit blocks 15 and 16 in FIG. In the above example, these components 15 and 16 are constructed by using a bipolar / MIS transistor composite driver circuit as shown in FIG. If this configuration is used, the outputs H and L of 15 and 16 are almost equalized by the operation of φ _P and Q ₁₅ during standby or during data line precharge. Potential, and when SA1 is driven φ _SA1 , ▲ ▼, 15,
By the operation of 16, H becomes 0V, L becomes the potential of V _EE , and SA
By the operation of L, all the data line pairs become 0 V on the high potential side and V _EE level on the low potential side. In this way, the composite driver circuits 15 and 16 with bipolar and MIS transistors can drive SA1 and then the data line pair at high speed, but on the other hand, when the data lines are driven at high speed and with high amplitude using bipolar transistors, the data lines are filled.・ Power consumption and peak current increase due to discharge. Since the number of data line pairs is as large as 512 pairs (1024 lines) in the case of a 256K bit memory, the peak current due to charging / discharging of the data lines increases to near 150 mA. Therefore, the following method is proposed to reduce the data line signal amplitude in order to reduce the power consumption and peak current while keeping the memory access time and cycle time high. For this purpose, refer to H in Fig. 44.
It is necessary to lower the high potential of the line or raise the low potential of the L line. First, a simple method of lowering the high potential of the H line is to omit the p-channel MIS transistor Q ₃₄ in the block 15 in FIG. As a result, the high potential of the H line drops by 1V _BE to -0.8V.

A simple way to raise the low potential of the L line is to omit the N channel MIS transistor Q ₃₇ of block 16 in FIG. As a result, the low potential of the L line is V _EE + 1V _BE -4.
It becomes 5V. Next, other methods for changing the potentials of the H line and the L line will be described using examples. Figure 45 shows block 15 in Figure 44.
Is a modified embodiment of the present invention, which is characterized in that the bipolar transistors Q ₄₁ and Q _{42 have} a Darlington connection configuration. The high potential of the output H line is -2V _BE -1.6V. Further, because of the Darlington connection configuration, the driving capability of the load H line is higher than that of the block 15 in FIG. 44, and the rise time of the H line is shortened. As a result, the data line signal has a high potential of -1.6.
V, low potential becomes V _EE and the amplitude decreases to about 70%. Therefore, the power consumption and the peak current due to the charging / discharging of the data line can be reduced to about 70% correspondingly. Although not shown in the figure, the number of bipolar transistors is 3
The high potential of the H line can be changed to V by connecting multiple stages or more or by using a diode for level shifting.
Obviously, it can be reduced by any integer multiple of _BE . Unlike FIG. 45, in FIG. 46, the internal power supply circuit 21 is used to lower the high potential of the H line, and this output is supplied to the source of the p-channel MIS transistor Q ₄₃ . By lowering the output potential of the circuit 21 below 0V, the high potential of the H line can be lowered. At this time, the driving capacity of Q ₄₃ decreases, but the load is the base of Q ₄₄ and is relatively light. Since the load of the H line is driven by the bipolar transistor Q ₄₄ , the decrease in speed at the time of rising of the H line is slight, and a speed equivalent to that in FIG. 44 can be obtained. The circuit block 21 of FIG. 46 reduces the fluctuation of the output potential due to the fluctuation of the load current. That is, it is necessary to reduce the output impedance, and it is preferable to use a bipolar transistor. Figures 47 and 48 are
46 is an embodiment of block 21 in FIG. Output potential V in FIG. 47
₂₁ is Becomes If the value of R ₂₁ / R ₂₂ is adjusted, V ₂₁ can be freely set as long as it is lower than −V _BE . The current source I ₂₁ has a role of reducing a potential change due to a load current variation of V ₂₁ , but it can be omitted. FIG. 48 shows a level shift circuit using a diode. Although two diodes are used in the figure, any number can be used. The role of the constant current source I ₂₂ is I
Same as ₂₁ , which has the effect of lowering the output impedance, but can be omitted. Obviously, a resistor may be inserted between V ₂₁ and V _EE instead of the constant current sources I ₂₁ and I ₂₂ .

Next, an embodiment in which the block 16 is modified in order to increase the potential of the L line in FIG. 44 is shown in FIGS. 49 and 50. FIG. 49 shows a Darlington connection structure of bipolar transistors for driving the L line. Low potential of L line is V _EE + 2V _BE
It becomes −3.8V. Further, in FIG. 50, a diode is connected in series between the L line and the bipolar transistor to obtain the L line low potential of the upper and word lines. In FIG. 51, a circuit block 22 for potential clamping is provided between the emitter of the bipolar transistor and V _EE . When this potential is V ₂₂ , the low potential of the L line is V ₂₂ + V _BE . As a concrete circuit of this block 22, there are the embodiments shown in FIGS. 52 and 53. In Fig. 52, the potential of V ₂₂ is Therefore, if the value of R ₂₃ / R ₂₄ is adjusted, an arbitrary value of V _EE + V _BE or more can be obtained. In FIG. 53, it is clamped by a diode and V ₂₂ = V _EE + 2V _BE is obtained. If the number of diodes is changed, an arbitrary integer value other than 2 is possible.

In this way, the idea of changing the output power voltage by changing the applied power supply voltage of the bipolar / MIS transistor composite circuit can be widely applied not only to driving the data line but also to other circuits. This is because the load drive capacity is MI depending on the power supply voltage.
This is due to the excellent properties of the bipolar and MIS transistor composite circuit, which does not change significantly compared to the circuit using only S transistors.

The first application of this idea to general memory peripheral circuits is
54 is a figure. The block 23 is composed of a bipolar and MIS transistor composite gate circuit or a composite driver circuit, and the output of the limiter power supply circuit of 24 on the positive side and 25 on the negative side is used as an applied voltage for its operation. With this limiter circuit, the effective power supply voltage applied to the block 23 can be lowered, and the signal amplitude generated therefrom can be reduced. As a result, the power consumption and peak current of the entire circuit system can be reduced. For the limiter circuit of the blocks 24 and 25, the circuit configurations shown in FIGS. 47, 48, 52 and 53 can be used. The limiter circuit using these bipolar transistors has an excellent property that the output impedance is small and the output potential does not easily change even if the current flowing through the block 23 changes.

While using a low-amplitude bipolar or MIS transistor composite circuit or bipolar circuit as shown in Fig. 54 for the memory buffer circuit, decoder circuit, etc., the word line is driven to a high amplitude while speeding up and reducing power consumption. It is possible to increase the memory cell storage voltage.

The word line signal W and other control signals in the memory tape described so far have been described by making certain assumptions as shown in the figure for the MIS to be applied and the conductivity type of the bipolar transistor. If the conductivity types are reversed, the polarities of the signals are also reversed. For example, if the MIS transistor of the memory cell is N
When the channel is changed from the P channel to the P channel, the word line is selected at a low potential and deselected at a high potential. Such changes are easy for those skilled in the art. Also, mutual change between ECL and TTL can be easily done as described above.

As described above, by applying the present invention in combination with a dynamic type semiconductor memory including a bipolar transistor in a part of the peripheral circuit, the data line precharge necessary for the operation of the dynamic type memory and all the word lines accompanying it are applied. Various functions, including non-selected functions, can be performed under the control of a single external input signal.

Thus, it is possible to realize a bipolar-MIS transistor composite dynamic semiconductor memory having both high integration of the dynamic memory cell and high speed of the peripheral circuit including the bipolar transistor.

〔The invention's effect〕

According to the present invention, by activating the read preamplifier SA2 before the rewrite amplifier SA1, it is possible to read the dynamic memory at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of a dynamic semiconductor memory having a dynamic memory cell and a peripheral circuit including a bipolar transistor, FIG. 2 is a circuit diagram excluding a write circuit around the memory cell, and FIG. FIG. 4 is an operation waveform diagram of the circuit of FIG. 4, FIG. 4 is a circuit diagram showing a writing circuit, FIG. 5 is an operation waveform diagram of the circuit of FIG. 2, and FIG. 6 is a modification of FIG.
FIG. 7 is a circuit diagram showing an embodiment of a decoder circuit having a function of deselecting all word lines (reset function) and a function of fixing selection / non-selection of word lines (latch function). Figure, Figure 8 is the operation waveform diagram,
FIG. 9 is a circuit diagram showing an example in which the 4-input NAND circuit in FIG. 7 is configured using CMOS, and FIG. 10 is a 2-input NAND gate driver circuit in FIG. 7 in a bipolar / MIS transistor composite circuit. Fig. 11 is a circuit diagram showing a configuration example, Fig. 11 is a circuit diagram showing a word driver circuit, and Fig. 12 is a block diagram showing an example of a circuit system in which the control signals φ _R and φ _L in Fig. 7 are made from ▲ ▼ input signals. , FIG. 13 is an operation waveform diagram thereof. FIG. 14 is a circuit diagram showing a second embodiment of a decoder circuit having a word line signal reset function and a latch function, FIG. 15 is its operation waveform diagram, and FIG. 16 is a more specific version of FIG. At ECL
FIG. 17 is a circuit diagram showing a circuit suitable for the interface, FIG. 17 is a circuit diagram for making the control signals φ _R and φ _L in FIG. 16 from ▲ ▼ inputs, FIG. 18 is an operation waveform diagram thereof, and FIG. Figure is a circuit diagram showing the logic circuit when the word line signal reset function is built into the word driver circuit. Figure 20 is its operation waveform diagram.
21 and 22 are two circuit diagrams of a bipolar and MIS transistor composite type driver circuit which realizes the logical function of FIG. 19, and FIG. 23 shows four decoder circuits and word driver circuits arranged in parallel with word lines. FIG. 24 is a circuit diagram showing a logic circuit having a word line reset function in a decoder circuit. FIG. 24 is a logic circuit in which four word driver circuits with a word line reset function are arranged in parallel with the word line by sharing the decoder circuit for four words. Fig. 25 is a circuit diagram of the ECL interface type address buffer circuit with a latch function, Figs. 26 and 27 are circuit diagrams showing a TTL interface type address buffer circuit with a latch function, Fig. 28. Is a block diagram showing the generation method of the control signal φ _{L in} FIGS. 25 to 27, and FIG.
It is an operation | movement waveform diagram of the circuit of the figure. Figure 30 is a logic diagram of the address buffer circuit incorporating the word line reset function.
The figure shows the operation waveform diagram, and FIGS. 32 and 33 show two concrete examples of the configuration of the ECL interface type address buffer circuit which realizes the logic of FIG. 30 and has the function of cutting off the power in the standby state. Circuit diagram, Fig. 34 shows X system address, Y
Operation waveform diagram showing memory control when switching both system addresses,
FIG. 35 shows the control signals φ _P , φ _SA1 , ▲ in FIGS. 2 and 6.
A block diagram showing the generation method of ▼, FIG. 36 is its operation waveform diagram, FIG. 37 is a conceptual diagram showing the generation method of the control signal φ _RW and write data I of the write circuit, and the control signal φ 1 _NV of the output circuit, FIG. 38 is an operation waveform diagram of the control signal around the memory cell at the time of writing, FIGS. 39 and 41 are output circuit diagrams of the ECL interface, and FIG. 40 is an operation waveform diagram thereof.
FIG. 42 is a circuit diagram showing a configuration example of a TTL interface and tri-state type output circuit, FIG. 43 is an operation waveform diagram thereof, FIG. 44 is a circuit diagram showing a drive circuit of a sense amplifier and an active restore circuit, 45 and 46 are circuit diagrams showing a modified example of the drive circuit 15 in FIG. 44, FIGS. 47 and 48 are circuit diagrams of the block 21 in FIG. 46, FIGS. 49 and 50. And FIG. 51 is a circuit diagram showing a modified example of the drive circuit 16 in FIG. 44,
52 and 53 are circuit diagrams of the block 22 shown in FIG.
FIG. 54 is a conceptual diagram of a bipolar / MIS transistor composite circuit system having a limiter power source, and FIGS. 55 and 56 are circuit diagrams showing conventional memory cells. X _{0 to} X _n ...... X system address input, Y _{0 to} Y _m ...... Y system address input, ▲ ▼ …… Chip select input, ▲ ▼
...... Write control input, DI ...... Write data input, DO ......
Read output, 2,2A, 2B ... Dynamic memory cell, 5
X, 5Y ... Address buffer circuit, 6 ... Memory cell array, 7 ... Write / read circuit, 8X, 8Y ... Decoder
Driver circuit, 9 ... Write / read control circuit, 10 ...
Output circuit, 11 ... Sense circuit, 11S ... Sub sense circuit, 12 ... Write circuit, 12S ... Sub sense circuit, W, W ₀ ,
W ₁ , W ₂ , W ₃ , W ₅₁₁ …… Word line, D, D ₀ , ▲ ▼, D ₁ , ▲
▼, D ₂ , ▲ ▼ …… Data line, SA1 …… first differential amplifier, SA2 …… second differential amplifier, O, …… sense circuit output, HP …… precharge circuit, 15,16… … Drive circuit for the first differential amplifier SA1, φ _SA1 , ▲ ▼ …… Drive circuit
15, 16 control signals, φ _P ... precharge circuit drive signal,
φ _Y0 , φ _Y1 , φ _Y2 …… Column selection signal, V _N …… Precharge voltage, I, …… Write data line signal, φ _RW …… Write circuit gate control signal, t _C …… Cycle time, φ _R ▲
▼ …… Reset signal, φ _L …… Latch signal, V _A ……
Address buffer output, Delay, Delay1, Delay2, Delay3, D
elay4, Delay5, Delay6, Delay7 ... delay circuit, LS, LS ₁ , L
S ₂ , LS ₃ …… Level shift circuit, (x ₀ , x ₁ , x ₂ ) …… x ₀ , x
₁ , x ₂ address buffer circuit output, (x ₃ , x ₄ , x ₅ ) ...
x _3, x _4, x ₅ address punishment Hua circuit _{output, (x 6, x 7,} x 8) ...
... x ₆ , x ₇ , x ₈ address buffer circuit output, V _CSA , V _CSB ...
… Constant current source drive voltage, 8X1,8X15 to 8X18 …… X decoder circuit, 8X2,8X21 to 8X24 …… Word driver circuit, φx ₀ 〜
φx ₃ ...... word driver circuit control signal, V _BB, V _BB1, V
_BB2 …… Reference voltage, V _EE …… ECL circuit power supply voltage, standard −5.
2V, V _CC ... TTL circuit power supply voltage, standard 5V, x, ... X address _buffer circuit output, φ _1NH ... output circuit control signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Noriyuki Homma Inventor Noriyuki Honma 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Kunihiko Yamaguchi 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Kiyoo Ito 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-58-91600 (JP, A) JP-A-59-229784 ( JP, A) JP 47-63332 (JP, A) JP 59-210589 (JP, A)

Claims (3)

[Claims] 1. A dynamic memory cell for storing information, a word line for accessing the dynamic memory cell, a data line for transmitting information stored in the dynamic memory cell, and a data line connected to the data line, A rewriting amplifier for rewriting information read from the dynamic memory cell to the dynamic memory cell, and senses the information from the dynamic memory cell connected to the data line and read to the data line. Connected to the output of the read preamplifier, a common write data line connected to the data line, a write switch for transmitting write data from the common write data line to the data line, And a read common data line, The read preamplifier includes a MOS transistor whose gate is connected to the data line and whose drain or source is connected to the read common data line.
Information is transmitted according to the magnitude of the current flowing in the source / drain path of the transistor, and the write switch includes a MOS transistor whose source / drain path is connected between the write common data line and the data line. Then, the selection signal for selecting the word line and the selection signal for activating the read preamplifier are input at substantially the same timing, and when reading information to the read common data line, the read preamplifier is A semiconductor memory device characterized by being activated first. 2. The semiconductor memory device according to claim 1, wherein when writing information from the write common data line to the data line, the write switch is turned on after activation of the rewrite amplifier. A semiconductor memory device characterized by being brought into a state. 3. The semiconductor memory device according to claim 1, wherein the read common data line has a magnitude of a current flowing through a source / drain path of a MOS transistor of the read preamplifier. A semiconductor memory device, to which a load for converting the voltage into a voltage is connected.