JPS5891600A - Memory circuit - Google Patents

Abstract

PURPOSE:To shorten a delay time of a circuit system, by constituting so that a function for selecting a specified digit line corresponding to an addres signal, and a function for simultaneously selecting all digit lines by a selecting signal, irrespective of an address signal can be switched. CONSTITUTION:An address signal takes one of the first level with is higher than reference voltage, and the second level which is lower than said voltage. A selecting signal takes one of the third level which is higher than this first level, and the fourth level which is lower than the reference voltage. When the selecting signal is in the fourth level, only one line of 4 buffer output lines 3-6 becomes low potential which is selecting potential of a digit line, and a pair of digit lines are selected. When the selecting signal is in the third level, the potential of the output lines 3-6 becomes all low potential, all the digit lines are selected, and all memories on the selected word line can be read out simultaneously. In this way, a delay time of a circuit system is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION The present application relates to a memory circuit, and particularly to a memory circuit suitable for a memory using a semiconductor.

The selection of digital and digital wires in conventional memory integrated circuits is
It is composed of a decoder circuit that selects one from a plurality of digital and digital lines.

However, in such conventional memories, in order to read all the memory cells at the intersections of the same word line and all the digit lines that intersect with it, the read operation must be repeated as many times as there are digit lines. Must be. Therefore, the time required to read all memory cells that intersect with the same word line becomes significant. It is an object of the present application to solve the problems of the prior art and provide a b-memory in which all memory cells connected to the same word line can be read in one read operation.

The present application resides in a memory circuit configured such that a selection signal can switch between a conventional function of selecting a specific digit line corresponding to an address signal and a function of simultaneously selecting all digit and digit lines regardless of the address signal. .

FIG. 1 shows an embodiment of the present application. Here, a pibo having four pairs of digit lines 13 and a plurality of word lines 11, -
RAM memory is shown. However, for simplicity, only one word line is shown. Furthermore, a flip-flop type memory cell 12 is provided at the intersection of these lines. A signal for designating the digital and digital line pair 13 to be selected is input to the address signal input terminals 1 and 2, and the row, pin and fgamma circuits 20 and 30 are driven by this signal. Here, circuits 20 and 30 have exactly the same configuration.

The outputs of circuits 20 and 30 are multi-emitter transistors Q
The buffer output lines 3 to 6 are driven through the buffer output lines 2 to Q. Terminal 7 is an input terminal for a selection signal, which is input to circuit 20.30 via buffer circuit 40, and input to the pace of TRQs.

The address signal is generated by the reference voltage generation circuit 8, and
The first voltage higher than the reference voltage applied to the paces of a, Q, and a.
level or a second level lower than this reference voltage. The selection signal takes either a third level higher than this first level or a fourth level lower than the reference voltage. The address signal is applied to the pace of TRQ□. The emitters of these TRQl, Q, and the emitters of TRQ, . . . -Qs are commonly connected to a constant current source 9.10, respectively. Now, when the selection signal is at the fourth level, the transistor (TR) Qs does not affect the output of the buffer circuit 20, and the first address signal to the terminal l is at the first or second level. TRQz and Qs connected to the buffer circuit 20 each attempt to output a high level (H level) or low level (L level) signal depending on whether or not the buffer circuit 20 is connected to the buffer circuit 20. In exactly the same way, T'RQ4 and QS connected to the buffer circuit 30 output H level or L level signals depending on whether the second address signal input to terminal 2 is at the first or second level. do. TRQ2 to Qs are wired-ORed as shown. After all, the output lines 3 to 6 are the first. The combinations of levels of the second address signals are respectively (second, second),
(No. 1. No. 2).

It becomes L level only when (2nd, 1st) and (1st. 1st). In this way, when the selection signal is at a lower potential than the reference voltage, only one of the four output lines 3 to 6 has a low potential, which is the selection potential of the output digit line, depending on the polarity of address signals 1 and 2. . That is, only one pair of digit lines is selected as in the conventional case.

On the other hand, when the selection signal is at the third level, all currents in current sources 9 and 10 flow from transistor Qs, and resistor R1
Due to the potential drop at , all the output signals of TRQZIQS become low potentials, which are the selection potentials of the digital y) lines. Here, the resistor R1 is selected to be equal to the collector resistances of TRQt and QB, and the current capacities of the current sources 9 and 10 are both equal.

In exactly the same way, all outputs of TRQ4*Q6 also become low potential. Therefore, the potentials of outputs II3 to II6 are all low potentials. Therefore, all digital and ) lines are selected. The feature of the present invention is that it has a function of rapidly switching from the selected state of l pairs of digit lines to the selected state of all digit lines to the line selected number by means of the selection signal.

Next, it will be briefly explained that the digital and ) lines are not selected when the buffer output line is at a high potential, but are selected only when the buffer output line is at a low potential.

Output line 3 is connected to the corresponding digit line via T RQ 2o and Qso'. Output lines 4 to 6 also correspond to each other via TRs, which are abbreviated with O marks. Connected to digit line. 134 digit lines T RQs
, Q7, the read reference signal is connected to terminal 14.1.
Given from 5. In the figure, these TRQs.

Only one set of Q7 is shown, and the others are abbreviated with an O mark.

In a state where a driving voltage is applied to one of the word lines 11, if the potential of the output signal line 3 is higher than the potential of the driven word line 11, the read current Io in the current source 18 flows through the transistor. Since the signal flows from Q20 and Q10, reading of the methyl cell 12 is not performed. However, (the potential of the rough γ output signal line 3 is driven by the word line 1)
When the potential becomes lower than the potential of 1, the read reference signal line 14
and the potential of 15 and the transistor Q40 constituting the cell.
The pace potentials of Qso and Qso are compared, and a pair of read currents 1. One of them flows from either TRQ45 or Qso of memory cell 12, and the other one flows from either read transistor Q7 or Qs. For example, a pair of read currents 1. from Q10 and from Q7. Each of them flows. Read transistor Q6. Q
A data signal is obtained by detecting which of y is conductive by the sense circuit 16. Sense circuit 16
is provided for each digit line pair 13. For simplicity, only the portion connected to one digital and digital wire 13 is shown in the figure. TRQ determines whether current flows through TRQ.
It is detected by the level of EMI of Q100 and RI15.

FIG. 2 shows another embodiment of the present application. In particular, the buffer circuits 20A and 30A are the same as the buffer circuit 20. in FIG.
Different from 30. When the selection signal input to terminal 7 is at a low potential, the transistors Ql and Qm are connected as in the conventional case.
) becomes conductive, and one of the output lines 3 to 50 becomes low level and the others become high level in response to the address input signal. When the selection signal is at a high potential, transistors Qs and Qs conduct and all output lines 3 to 3 are turned on, regardless of the address input signal.
6 is a low potential.

As described above, a specific memory cell or a plurality of memory cells from among the memory cells connected to the same word line are selected depending on the level of the selection signal.

In this way, the memory cell group, comparison circuit, parity check circuit, etc. are integrated on the same chip.
In the case of Memory (functional memory), unlike conventional methods, all digit lines are selected at the same time, and the stored information of all memory cells selected by the word line is simultaneously read out and used as input signals to comparison circuits, parity check circuits, etc. This makes it possible to shorten the delay time of these circuit systems.

[Brief explanation of the drawing]

Claims (1)

[Claims] A plurality of word lines, a plurality of digit lines, a memory cell provided at the intersection of each word line and digit line, a detection circuit connected to each digit line, and a word for selecting the plurality of word lines. A memory having a line drive circuit and a digit line drive circuit for selecting a digit line, and for selectively reading memory cells located at intersections of a selected word line and a digit line, The detection circuit is composed of a plurality of circuits, each of which is provided corresponding to each digit, and outputs a storage signal of a memory cell connected to each digit line, and the digit line drive circuit outputs an address signal. and means for selectively driving a digit line corresponding to the address signal in response to the first selection signal; and means for selectively driving a digit line corresponding to the address signal in response to the second selection signal; and means for driving a power line.