JPH0143397B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static RAM (random access memory) composed of bipolar transistors.

Prior to this invention, a bipolar RAM write/read method using three-value voltages was proposed.

In this three-value method, for the storage information of the high level V _CH and low level V _CL of the selected memory cell, a reference potential V refc for the read operation set to an intermediate voltage between the two and a reference potential V _refc for the write operation are set to the intermediate voltage between the two. A ternary voltage with a high level write voltage V _WH set to a voltage higher than the above high level V _CH and a low level write voltage V _WL set to a voltage lower than the above low level V _CL is applied to the write circuit. This is how it is formed.

As such a three-value write circuit, a circuit as shown in FIG. 1 was considered prior to the present invention.

In this circuit, two sets of differential transistors Q ₁ and Q ₂ each have a constant power supply I ₀ on their common emitters.
A three-value voltage is formed by Q ₃ and Q ₄ and resistor circuits R ₁ to R ₃ provided at their collectors, and output voltages V ₁ and V ₂ are obtained through an emitter follower circuit.

During writing, one input signal D _IN (or _IN ) is set to high level according to the write data with respect to the reference voltage V _BB , so the voltages V _WH and V _WL are calculated by the following equation (1). , given by (2).

V _WH = −2R ₁ I ₀ −V _BE …(1) V _WL =−2(R ₁ +R ₂ )I ₀ −V _BE …(2) Also, when _reading , both Since both the input signals D _IN and _IN are set to low level, the voltage V _refc is determined by the following equation (3).

V _refc = - (2R ₁ + R ₂ ) I ₀ - V _BE (3) Therefore, as shown by _{the solid line} in Fig. 2, the above voltages V _WL and V _WL are It is vertically symmetrical.

Here, in order to realize high-speed writing to memory cells, the resistance values of resistors R ₂ and R ₃ are increased to increase the low-level write voltage V _WL , as shown by the dotted line in the figure. When the resistance value of R ₁ is decreased,
The high level write voltage V _WH also increases.

When the high-level write voltage V _WH increases, the base voltage of the output transistors Q ₈ and Q ₉ increases,
These transistors Q ₈ , Q ₉ and their emitters are coupled to data line D (or) to saturate a memory cell read/write transistor (not shown) receiving said output voltage V ₁ (V ₂ ). , it actually slows down the access time to the memory cells.

In other words, when transitioning from writing to reading state,
This is because the fall of the voltage _VWH is significantly delayed.

An object of the present invention is to provide a bipolar RAM that operates at high speed.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 3 shows a circuit diagram of an embodiment of the present invention. The RAM shown in the figure is formed on one semiconductor substrate by a known semiconductor manufacturing method. Terminals XA ₀ to XA _k , YA ₀ to
YA _l , D _OUT , D _IN , and −V _EE , GND are
It is considered as its external terminal.

As one of the memory cells is shown as a specific circuit, the memory cell is composed of npn drive transistors Q ₁₂ and Q ₁₃ whose bases and collectors are cross-connected to each other, and each of which is connected to the collector, although it is not particularly limited. A flip-flop consisting of pnp load transistors Q ₁₄ and Q ₁₅ is used. The drive transistors Q ₁₂ and Q ₁₃ have a multi-emitter structure, although not particularly limited, and one emitter is shared and connected to a constant current source (not shown) that forms a holding current _Io . The other emitters of the transistors Q ₁₂ and Q ₁₃ are connected to a pair of data (or called digit) lines D 0 and D ₀ , respectively.
Connected to D ₀ .

Note that the transistors Q ₁₂ and Q ₁₃ may each be constituted by two transistors having a common base and collector.

Further, the load transistors Q ₁₄ and Q ₁₅ may be replaced with resistors and clamp diodes.

The common emitters of the load transistors Q ₁₄ and Q ₁₅ are connected to the word line W ₀ .

Centering around the memory cell shown as a representative, ^2l similar memory cells are arranged in a horizontal row, using the word line _W0 in common.

Further, in a vertical column, 2 ^k similar memory cells are configured with data lines D ₀ and ₀ in common. In such columns and rows, 2l ^+k memory cells are arranged in a matrix, forming a memory array M-
ARY is configured.

The representative word lines W ₀ and W _2k are selected/unselected by word line drive transistors Q ₁₆ and Q ₁₇ which receive the X address decode signals X ₀ and X _2k . These X address decode signals X ₀ to X _2k are formed by an X address decoder.

Address signals supplied from a suitable circuit device (not shown) are connected to address input terminals XA ₀ to XA _k
The address buffers XB ₀ to XB k are entered through the address buffers XB 0 to XB _k . The address buffer XB ₀ to XB _k is
Since a complementary address signal corresponding to the input address signal is formed and transmitted to the X address decoder, one word line selection signal is formed here.

A pair of representative data lines D ₀ , ₀ are transistors Q ₁₈ , Q ₂₀ as column switches.
It is connected to a constant current source I _R provided in common to other data lines as well. A Y decode signal Y ₀ formed by a Y decoder is applied to the bases of these transistors Q ₁₈ and Q ₂₀ .

Address signals supplied from suitable circuit devices (not shown) are input to address buffers YB ₀ to YB ₁ via address input terminals YA ₀ to YA ₁ . The above address buffer YB ₀ to YB _l is
Since a complementary address signal corresponding to the input address signal is formed and transmitted to the Y address decoder, a pair of word line selection signals are also formed here.

In this embodiment, although not particularly limited, the following circuit is provided in order to apply a predetermined bias voltage to the data line when not selected.

A diode _D4 connected in series and a resistor are provided between the base and collector of the transistor _Q21 whose collector is grounded. The series diode and resistor are connected to a constant current source _IR similar to the above through a transistor _Q19 similar to the column switch transistor. In addition, the emitters of the transistor Q ₂₁ are connected to a pair of data lines, respectively.
Connected to D ₀ , ₀ . Therefore, the transistor _Q21 has a multi-emitter structure or is composed of two transistors having a common base and collector.

Furthermore, a minute constant current source is provided in the pair of data lines D ₀ and ₀ . That is, constant voltage
Since the transistors Q ₂₂ and Q ₂₃ receiving V _B and their emitter resistances constantly sink a small constant current, the data line potential when not selected is approximately equal to the forward voltage V _F of diode D ₄ . transistor Q ₂₁
It is biased by the base and emitter voltage _VBE .

For writing/reading to/from memory cells, the pair of data lines D ₀ , ₀ are provided with write/read transistors Q ₁₀ , Q ₁₁ whose emitters are coupled. The collector output signals of these transistors Q ₁₀ and Q ₁₁ are transmitted to the input of the sense amplifier SA.

Although not particularly limited, this sense amplifier SA is composed of the following circuit elements.

The collectors of the transistors Q ₁₀ and Q ₁₁ are connected to the emitters of transistors Q ₂₄ and Q ₂₅ that receive a constant voltage formed by a resistor R ₆ connected in series with a constant current source. These transistors Q ₂₄ ,
The emitters of _Q25 are each provided with a constant current source, and the collectors thereof are provided with resistors _R4 and _R5 , respectively. And the above transistor Q ₂₄ ,
The collector output of Q ₂₅ is the transistor Q ₂₆ , Q ₂₇
The signal is transmitted to an emitter follower circuit composed of level shift diodes D ₁ and D ₂ provided at the emitter and a constant current source. Above diode
The output signal through D ₁ and D ₂ is transmitted to a data output buffer DOB composed of an ECL circuit.

Furthermore, the output voltages V ₁ and V ₂ of the write circuit WA are applied to the bases of the transistors Q ₁₀ and Q ₁₁ .

The write circuit WA is constituted by the following circuit elements as shown in the figure.

Although the write circuit of this embodiment is not particularly limited, a three-value voltage is formed by three sets of differential transistor circuits. A constant current source I ₀ is provided at the common emitters of the differential transistors Q ₁ , Q ₂ and Q ₃ , Q ₄ . The collectors of transistors Q ₁ , Q ₃ and Q ₂ , Q ₄ are each shared. Furthermore, a constant current source I ₀ ' is provided at the common emitters of the differential transistors Q ₅ to Q ₇ .
The collectors of the transistors Q ₅ and Q ₆ are
The collectors of the transistors Q ₁ , Q ₃ and Q ₂ , Q ₄ are also shared, respectively, and the collector of the transistor Q ₇ is grounded.

The resistor R ₁ has one end grounded and the other end connected to the resistor
One ends of R ₂ and R ₃ are commonly connected. The other ends of these resistors R ₂ and R ₃ are respectively connected to the common collectors of the three sets of differential transistors. The resistance values of these resistors R ₂ and R ₃ are set equal.

At the bases of the transistors Q ₂ , Q ₃ and Q ₇ ,
A reference voltage V _BB is applied. Also, transistor
Signals D _IN and _IN from the data input buffer DIB are applied to the bases of Q ₁ , Q ₆ and Q ₄ and Q ₅ . The data input buffer DIB receives the write data from the external terminal D _IN and the write control signal ' from the control circuit CONT, and for example, as shown in FIG _. (or _IN ) to a higher level than the reference voltage _VBB . Furthermore, during reading, both signals D _IN and _IN are set to a lower level than the reference voltage VBB.

The collector output of the above differential circuit is a transistor
The above transistors Q ₁₀ and _{Q 11} are connected to each other through an emitter follower circuit composed of Q 8 and Q ₉ and a constant current source.
It is conveyed to the base of.

In the write circuit WA of this example circuit, a newly provided differential circuit (Q ₅ or
Q ₇ ) is a constant current because transistor Q ₇ is turned on.
I ₀ ′ flows through this transistor Q ₇ . Therefore, the reference voltage V _refc for reading is as shown in equation (3) above.
V _refc = - (2R ₁ + R ₂ ) I ₀ - V _BE .

Also, during writing, one input signal D _IN (or _IN ) is set to high level according to the write data with respect to the reference voltage V _BB , so transistor Q ₅ (or Q ₆ ) is turned on. , a constant current I ₀ ' is passed through the above resistance circuit, so the write voltages V _WH , V _WL are given by the following equation (4),
It is determined by (5).

For example, if D _IN is at a high level, transistors Q ₁ , Q ₃ and Q ₆ are turned on, so V _WH = - (2I ₀ + I ₀ ') R ₁ - I ₀ 'R ₃ - V _BE ... (4) V _WL = − (2I ₀ + I ₀ ′) R ₁ −2I ₀ R ₂ − V _BE …(5).

In this example circuit, compared to the circuit shown in FIG. 1, the voltage V _WH is suppressed to a lower level by the voltage drop across the resistors R ₁ and R ₃ due to the new addition of the constant current I ₀ '. The voltage V _WL is equal to the voltage drop of the above resistor R ₁ .
becomes low (large), so it becomes asymmetrical with respect to the voltage V _refc as shown in FIG.

Therefore, the transistors Q ₁₀ and Q ₁₁ are strongly turned off by the low-level write voltage V _WL , thereby realizing high-speed writing to the memory cell. On the other hand, since the high-level write voltage V _WH is suppressed to the necessary minimum, it does not saturate the transistors Q ₈ , Q ₉ and Q ₁₀ , Q ₁₁ , so that switching to the read operation after writing can be performed quickly. With these features, it is possible to speed up memory access.

In the above write circuit WA, transistors Q ₅ ,
If we connect the collectors of Q ₆ inversely to each other, we get
The write voltages V _WH and V _WL can be set as shown in the following equations (6) and (7).

V _WH = −(2I ₀ +I ₀ ′)R ₁ ―V _RE …(6) V _WL =−(R ₁ +R ₂ )・(2I ₀ +I ₀ ′)−V _BE …(7) Any of the above The selection of the addition method for the current I ₀ ' depends on the resistance values of the resistors R ₁ to R ₃ , the constant current value I ₀ ,
It can be freely determined by I ₀ ′.

FIG. 5A shows another embodiment of the write circuit WA.

In this example, the differential transistor Q ₃₀ or
A three-value voltage is formed by the combination of Q ₃₂ and differential transistors Q ₃₃ and Q ₃₄ . That is, since each voltage V _R , D _IN , _IN is set as shown in FIG. 5B, the transistors Q ₃₀ and Q ₃₃ are
turns on, the voltage V _refc is -R ₁ I ₀ - R ₂ I ₀ /2
is set to On the other hand, during writing, the transistor
Q ₃₄ turns on, Q ₃₀ and Q ₃₃ turn off, and transistor Q ₃₁ or Q ₃₂ turns on according to the write data, so the voltage V _WH = −R ₁ I ₀ is set, and the voltage V _WL = −
(R ₁ + R ₂ ) I is set to ₀ .

Then, as described above, the constant current I ₀ ' selectively flows through the resistor circuit during writing by the differential transistors Q ₅ ' to Q ₇ ', so the output voltages V ₁ and V ₂ are read out as the reference voltage as described above. It is possible to obtain a voltage asymmetric with respect to V _refc .

As described above, if the write circuit of the present invention is of the type that selectively adds a constant current as described above to a circuit that forms a symmetrical three-value voltage with respect to the read reference voltage V _refc , then what is wrong with it? Good too.

The present invention can be widely applied to bipolar RAMs that perform writing/reading using three-value voltages.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a write circuit considered prior to the present invention, FIG. 2 is an operation waveform diagram thereof, and FIG. 3 is a bipolar type RAM showing an embodiment of the present invention. 4 is an operation waveform diagram for explaining its operation, and FIG. 5A is a circuit diagram of a write circuit showing another embodiment of the present invention.
FIG. 5B is an input timing diagram thereof.

Claims (1)

[Scope of Claims] 1. A first resistor to which a reference potential is applied to one end, a second resistor provided between the other end of the first resistor and a first output point, and the above other resistors of the first resistor. a third resistor provided between the end and the second output point;
current switching means coupled to the second output point;
The current switching means applies the electric potentials of the first and second output points respectively to the reference electric potential determined by the voltage drop of the first to third resistors in the read operation. A first current is applied to one of the first and second output points to make one of the first and second output points go to a low level corresponding to write data and the other to a high level during a write operation. A bipolar RAM, characterized in that it is adapted to provide a second current at a level greater than the first current. 2. The current switching means includes a first differential transistor pair, one of which is turned on during a read operation and differentially operated by one of the complementary input signals during a write operation, and a common emitter of the first differential transistor pair. a constant current source coupled to the constant current source; a second differential transistor pair, one of which is turned on during a read operation and differentially operated by the other of the complementary input signals during a write operation; and the second differential transistor pair. a constant current source coupled to a common emitter of the third differential transistor pair; a third differential transistor pair, both of which are turned off during a read operation and differentially operated by a complementary input signal during a write operation; a constant current source coupled to a common emitter, the first and second differential transistor pairs determining the first current and determining the second current. Bipolar type according to claim 1, characterized in that:
RAM.