JPS6267790A - Static type ram - Google Patents

Abstract

PURPOSE:To improve an operation margin by forming a load means having comparatively small conductance, and write recovery MOSFETs to be temporarily driven at the end of writing operation and set up so as to have comparatively large conductance. CONSTITUTION:The load MOSFETs Q18, Q19 to be driven as a load means at the time of reading operation by supplying an internal control signal, the inverse of we, to a gate to improve the operation margin and set up to have comparatively small inductance are provided to a common complementary data lines CD, and the inverse of CD. The write recovery MOSFETs, Q20, Q21 to be driven by supplying an one-shot pulse phiwr formed to generate at the end of writing operation to a gate and set up so as to have comparatively large conductance are formed to attain rapid write recovery operation. Consequently, reading signals having comparatively large level difference between them can be obtained on the common complementary data lines and the operation margin of a sense amplifeir for amplifying the reading signals can be improved.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a static RAM (random access memory). It's about technology.

(7J Technology) A memory cell in a CMOS static RAM is provided between, for example, a launch circuit consisting of a CMOS inverter circuit whose inputs and outputs are cross-connected, and a pair of input/output terminals and a complementary data line. Transmission gate MOSFE
It is composed of T.

The complementary data lines are selectively coupled to a common complementary data line via a column switch circuit.

In a write operation, in order to invert the information stored in the latch circuit constituting the memory cell, the common complementary data line is connected to a low level such as the ground potential of the circuit formed by the write circuit and a low level such as the power supply voltage. High level is supplied. The low level in such a write operation needs to be quickly returned to a high level upon completion of the write operation in preparation for the next read operation. In order to shorten the write recovery time, the common complementary data line is provided with a load MOSFET having a relatively large conductance. However, in a read operation, the signal on the common complementary data line is
Since it is determined by the conductance ratio of the OS FET, column switch MOSFET, and each MOS FET constituting the memory cell, the load MO5
If the conductance of the FET is made relatively large, the level of the read signal on the common complementary data line will be reduced accordingly. Further, as the power supply voltage decreases, its level becomes smaller. A sense amplifier that amplifies such minute-level read signals needs to have a large gain. However, in a differential sense amplifier, if the element constants are set to obtain a large gain, , the influence of process variation is thickened (
Therefore, a problem arises in that the operating margin and power supply margin deteriorate.

Regarding the static type RAM, see, for example, Japanese Patent Laid-Open No. 198595/1983.

[Purpose of the invention]

An object of the present invention is to provide a static RAM with improved operating margin.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a pair of complementary data lines to which static memory cells are coupled are connected selectively via a column switch MOSFET, and as a load means provided on a common complementary data line, a comparison is made to obtain a read signal of a relatively large level. A load means having a relatively small conductance and a write recovery MOSFET having a relatively large conductance that is temporarily set to 5/h1 at the end of a write operation are provided.

(Embodiment) FIG. 1 shows a circuit diagram of an embodiment of the present invention. Although not particularly limited, the RAM in the figure may be a known CM
O3 integrated circuit technology is formed on a semiconductor substrate, such as a silicon single crystal (II).

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal N-type silicon. P channel MOS
The FET has a source region, a drain region formed on the surface of the semiconductor substrate, and a gate made of polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. Consists of electrodes. The N-channel MOS FET is formed in a P-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of P-channel MOSFETs formed thereon. The P-type well region constitutes the substrate gate of the N-channel MOS FET formed thereon. In addition,
A configuration in which MOSFETs constituting a memory cell are formed in a well region is effective in preventing erroneous inversion of stored information caused by α rays or the like.

The memory array M-ARY includes a plurality of memory cells MC arranged in a matrix, which are shown as a representative example.
It is composed of word lines WO to Wn and complementary data lines DO, DO to Di, DI.

Each of the memory cells MC has the same configuration as each other,
As one specific circuit is shown as a representative, it is an N-channel type circuit in which the gate and drain are cross-connected to each other and the source is coupled to the ground point GND of the circuit.
MOSFETQ1゜Q2 and the above MOSFETQ1. Q
2 and the power supply terminal Vcc. And the above MOSFETQ1. An N-channel type transmission gate MOSFET Q3.Q2 is connected between the common connection point of Q2 and the complementary data lines Do, DO. Q4 is provided. Transmission gate MC of memory cells arranged in the same row
5FETQ3. The gates such as G4 are commonly connected to the corresponding word lines WO to 'Nn etc. shown as examples, and the input/output terminals of the memory cells arranged in the same column are as follows.
A corresponding pair of complementary data lines (bit lines or signals) 9 DO, Do and DI, each illustratively shown.

It is connected to Dl etc.

In the memory cell, MC5FETQ1. G2 and the resistors R1 and R2 form a kind of flip-flop circuit, but the operating point in the information retention state is quite different from that of a frimbuff circuit in the ordinary sense. That is, in order to make the memory cell MC low in power, its resistor R1 sets the gate voltage of MC3FETG2 to a voltage slightly higher than its threshold voltage when MC5FETQ1 is turned off. The resistance value is set to a significantly high value that can be maintained.

Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistors R1 and R2 have high resistances that can compensate for the drain leakage currents of the MOS FETQ1 and G2. Resistors R1 and R2 are the gate capacitance (
It has enough current supply ability to prevent the information charges stored in the memory cell (not shown) from being discharged.

According to this embodiment, even though the RAM is manufactured by CMO3-IC technology, the memory cell MC is made up of an N-channel MOSFET and a polysilicon resistance element as described above.

The memory cell and memory array of this embodiment are made of P-channel MOS F E instead of the polysilicon resistance element described above.
Compared to the case where T is used, the size can be made smaller. That is, when using a polysilicon resistor, the drive MO5F
It can be formed on the gate electrode of ETQI or G2, and its size can be reduced. Then, like when using a P-channel MOSFET, the drive MOS
Since FETQl and G2 do not have to be separated by a relatively large distance, no wasted blank space is generated.

In the figure, each complementary data line DO, DO and DI, D
Between i and the power supply voltage Vcc, there are N-channel type load MOSFETs Q7 to 0, which act as resistance elements by constantly supplying the power supply voltage Vcc to their gates.
．． 10 are provided.

In the figure, the word line Wo is connected to the X address decoder
-DCR is selected by the output signal formed by the /7 (NOR) gate circuit G1. This means that
The same applies to other word lines Wn.

The X address decoders X-DCR are mutually similar NOR gate circuits G1. Consists of G2 etc. The input terminals of these NOR gate circuits C1, G2, etc. receive an external address signal AX (an address signal output from an appropriate circuit device not shown) consisting of multiple bits.
Internal complementary address signals formed by address buffer X-ADB are applied in a predetermined combination.

A pair of complementary data lines DO, D in the memory array
O, Di, and Di are N for data line selection, respectively.
Channel type transmission cable Mo5FETQI 2. Ql
3 and G14. It is connected to common complementary data lines CD and CD via a column switch circuit composed of G15.

MC3FETQ12 that constitutes the above column switch circuit
．． G13 and G14. At the gate of G15, each Y
Selection signals YO and Yl formed by address decoder Y-DCH are supplied.

The Y address decoder Y-DCR includes NOR gate circuits G3. Consists of G4 etc. These NOR gate circuits G3゜04, etc. receive an internal complementary address signal formed by a Y address buffer Y-ADB that receives an external address signal AY (an address signal output from an appropriate circuit device not shown) consisting of a plurality of bits. are applied in a predetermined combination.

In this embodiment, the common complementary data lines CD, C
In order to improve the operation margin, D has a relatively small conductance that operates as a load means during a read operation by supplying an internal control signal τ to the gate, although it is not particularly limited. Load MO
SFETs Q18 and Q19 are provided. In addition, in order to realize a high-speed write recovery operation, a one-shot pulse φw is generated at the end of the write operation.
Write recovery MOSFETs Q20 and Q21 are provided which operate by supplying r to their gates and have relatively large conductance.

The common complementary data lines CD and CD are connected to the readout circuit RA.
The input terminal of the write circuit WA is connected to the output terminal of the write circuit WA. The read circuit RA sends a read signal to the data output terminal Dout, and the input terminal of the write circuit WA is
A write data signal is supplied from the data input terminal Din.

The read circuit RA includes a sense amplifier and performs a highly sensitive sensing operation. The operation of the read circuit RA is controlled by a typical control signal φr supplied from the control circuit C0NT.

The readout circuit RA differentially amplifies the data signals supplied to the common complementary data lines CD and CD when it is in an operating state, and outputs the amplified data signal to the data output terminal Dout. The readout circuit RA puts its output terminal into a high impedance state or a floating state when it is inactive.

The operation of the read-in circuit WA is controlled by a typical control signal φW, and when it is in the operating state, a complementary data signal corresponding to the input data supplied to the data input terminal Din is input to the common complementary data line. CD, output to CD. Write circuit WA puts a pair of its output terminals into a high impedance state or a floating state when it is inactive.

The timing control circuit TC receives control signals from the external terminals WE and C3, and outputs the internal control timing signals φr,
φW, φ-r, etc. are formed.

Note that, although not particularly limited, an equalizing MO5FET Q1 is provided between the paired complementary data lines Do, DI, and DI, and between the common complementary data lines CD, CD.
6. Q17 and Q22 are provided respectively. The equalize pulse φq generated by the address signal change detection ATD is supplied to the gates of these MOSFETs QI6, Q17, and Q22. The address signal change detection circuit ATD has address buffers XADB and YADB.
When one of the address signals ax and ay is changed, it is detected and one shot of pulse φq is generated. As a result, the memory access causes the complementary data lines Do and D to be activated by the pulse φq.

, Di, Dl and the common complementary data lines CD, CD are short-circuited. As a result, these complementary data lines DO, Do
, Dl, ]rl and the common complementary data lines CD, CD change from the same level in accordance with the information stored in the memory cell in a read operation, and in accordance with a write signal in a write operation, so that high-speed operation can be achieved.

Figure 2 shows the write recovery MOS FET.
A timing diagram is shown to explain the operation of Q20 and Q21.

Although not shown, when the chip selection signal C8 is set to low level and the address signals AX and AY are supplied,
When the write enable signal WE is set to a low level, the write circuit WA is activated. IF loading circuit WA
According to the write signal supplied from the external terminal Din, the common complementary data lines CD and CD are connected to the power supply voltage Vcc.
It conveys a high level write signal such as , and a low level write signal such as the ground potential of the circuit. Such a write signal is sent to the memory array M- through the column switch MOS FET which is activated according to the address signal AY.
The signal is transmitted to a pair of complementary data lines forming ARY. In this manner, the write signal transmitted to the complementary data line is transmitted to the memory cell coupled to the word line selected according to the address signal AX, thereby performing writing.

When the write enable signal WE is changed from low level to high level, the timing control circuit TO generates a write recovery pulse φ correction.

As a result, the write recovery MOS FETs Q20 and Q2 have relatively large conductance.
1 is turned on, and the above-mentioned low level writing (one of the common complementary data lines CD or CD to which No. 1 is transmitted is rapidly changed from low level to high level by 11).

〔effect〕

(1) By providing a write recovery MOSFET with a relatively large conductance and temporarily activating it at the writing end timing, the write recovery operation can be performed within a short time. As a result, in the read operation, the load MOSFET having a relatively small conductance is used without considering the write recovery operation.
T can be used. Therefore, since it is possible to obtain read signals having a relatively large level difference on the common complementary data lines, it is possible to obtain an effect that the operating margin of the sense amplifier that amplifies the read signals can be improved.

(2) According to the above (11), the gain of the sense amplifier can be set to be relatively small. This has the effect that the influence of process variations can be reduced and stable sensing operation can be performed.

(3) As a result of the above (11) increasing the level of the read signal, a sufficient read signal level can be obtained even if the power supply voltage is made relatively low.This has the effect of increasing the power supply margin.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, MO5FETs Q18 and Q19, which are made to have relatively small conductance and are operated during reading, have their gates constantly supplied with the power supply voltage Vcc, so that
It may also be adapted to operate as a resistance means. Therefore, the load means for reading is a MOS
In addition to FETs, resistance means such as polysilicon layers can also be used. The equalizing MOSFET and the address signal change exposure circuit may be omitted. Furthermore, the memory cell may use a static flip-flop circuit configured by combining a P-channel O3FET and an N-channel O3FET. The configuration can take various fourth embodiments.

[Application field]

This invention can be widely applied to static type RΔM.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of the present invention;
The figure is a timing diagram showing an example of the operation. M-ARY...) Mo') -f Ray, XADB・
-X address buffer, YADB...Y address buffer, XDCR...X address decoder, YDCR...
Y address decoder, MC...memory cell, WA...write circuit, RA...read/output circuit, TC...timing control circuit, ATD...address signal change detection circuit "Fl/JPEI-t-/J" J“1”5θ)\,1
・CD, CD Figure 18 LC

Claims (1)

[Claims] 1. A pair of complementary data lines to which a pair of input/output nodes of static memory cells are coupled, and a column switch MOSF that couples the complementary data lines to a common complementary data line.
ET and a load means provided on the common complementary data line, which has a relatively small conductance so as to obtain a relatively large level read signal, and a relatively large conductance which is temporarily activated at the end of the write operation. MOS for write recovery
A static type RAM characterized by including a FET.
. 2. The load means with relatively small conductance is a MOSFET operated by a read operation signal.
A static type RAM according to claim 1, characterized in that: