JPH0238823U

JPH0238823U -

Info

Publication number: JPH0238823U
Application number: JP11804588U
Authority: JP
Priority date: 1988-09-08
Filing date: 1988-09-08
Publication date: 1990-03-15

Description

[Brief explanation of drawings]

第１図は本考案の実施例を示す回路図、第２図
は第１図に示した本考案の実施例の動作を示す図
、第３図は第１図に示した素子１と２の他の例を
示す図、第４図は従来例を示す回路図、第５図は
第４図に示した従来例の動作を示す図である。ＶＤＤ，ＧＮＤ＝ＯＶ……電源電圧、ａ，ｂ，
ｃ……各インバータ、ＶＩＮ……入力電圧、ＶＯ
ＵＴ……出力電圧、１，３，５，７……Ｎチヤネ
ルＭＯＳ・ＦＥＴ、２，４，６，８……Ｐチヤネ
ルＭＯＳ・ＦＥＴ、ＶＴ_ｎ……ＦＥＴｎのスレシ
ホールド電圧（ｎ＝１…）。 FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the operation of the embodiment of the present invention shown in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing another example, and FIG. 5 is a diagram showing the operation of the conventional example shown in FIG. VDD, GND=OV...Power supply voltage, a, b,
c...Each inverter, VIN...Input voltage, VO
UT... Output voltage, 1, 3, 5, 7... N channel MOS/FET, 2, 4, 6, 8... P channel MOS/FET, VT _n ... Threshold voltage of FETn (n=1 …).

Claims

[Scope of utility model registration request]

a first inverter that receives an input signal and is configured with a first transistor of one conductivity type and a second transistor of the other conductivity type, both of which are configured relative to each other between the first and second power supplies; In response to receiving an input signal, a third transistor of one conductivity type is placed on the first power supply side, a fourth transistor of another conductivity type is on the second power supply side, and a third transistor of one conductivity type is on the third transistor side. 5 transistors, the fifth transistor and the fourth transistor;
a second inverter comprising a sixth transistor of a different conductivity type between the transistors, and having its output terminal connected to the output terminal of the first inverter;
A seventh transistor of one conductivity type and an eighth transistor of the other conductivity type receive the output of each of the first and second inverters and transmit the output signal to each of the fifth and sixth transistors of the second inverter. In the Schmitt trigger circuit, the respective threshold voltages VT ₁ to VT ₄ of the first to fourth transistors are set such that VT ₁ , VT ₃ >0.
, VT ₂ , VT ₃ <0, where the power supply voltage between the first and second power supplies is VDD, VT ₁ >VT ₃ , |
VT ₂ |> | VT ₄ |, VT ₁ + | VT ₂ | ≧V
DD, VT ₁ + | VT ₄ |≒VDD, VT ₃ + |
A Schmitt trigger circuit characterized by _VT2 |≒VDD.