JP2008211720A - High hysteresis width input circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problems: though a conventional high hysteresis width input circuit changes the β ratio of the inverter circuit comprising P type MOSFET and N type MOSFET equivalently to make the hysteresis at the logic level, when the power-supply voltage decreases in this method, the hysteresis width extremely becomes small; the hysteresis width is less likely to be secured against a wide-range fluctuation in the power-supply voltage; and the operation of the circuit is susceptible to variations in the manufacturing process because the setting of a shape ratio is rather insufficient because the P and N type MOSFETs are employed for forming the logic level. <P>SOLUTION: The high hysteresis width input circuit includes: input inverter circuits, P and N type MOSFETs in a power source of a positive pole; N and P type MOSFETs in a power source of a negative pole; and a delay circuit for storing/delaying a preceding state even transiently. A hysteresis characteristic is obtained by turning ON/OFF the MOSFETs depending on a preceding state. The MOSFETs different in voltage characteristics are selectively used, thereby solving the problem. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  In a semiconductor integrated circuit device using an insulated gate field effect transistor (hereinafter abbreviated as MOSFET), the present invention provides noise when an input signal of an input circuit transits from a high potential to a low potential or from a low potential to a high potential. In order to eliminate malfunctions and instabilities due to noise, the circuit system has hysteresis characteristics at the logic level of the input circuit. In addition to the standard operating voltage, the hysteresis width can be increased even when the power supply voltage drops. The present invention relates to a circuit configuration that ensures a sufficiently large size.

  Conventionally, an input signal terminal of an integrated circuit, particularly a digital circuit, has a difference between the rising and falling edges of the input signal in the logic level for determining a signal change in order to eliminate malfunction and instability due to noise. The use of a hysteresis input circuit having hysteresis characteristics is widely performed. However, in recent years, when an integrated circuit is miniaturized and a low power supply voltage is used with a decrease in breakdown voltage, a sufficient hysteresis width cannot be secured.

The conventional circuit will be described below. An input circuit having a general hysteresis characteristic in a MOS integrated circuit using a conventional MOSFET constitutes a circuit equivalent to an inverter circuit, is always governed by an input signal, and is a major factor that determines its logic level. Two types of ratios of the conductance constant β _P of the type MOSFET and the conductance constant β _N of the N type MOSFET are provided, and the circuit configuration is such that the ratio of the two types of β _P and β _N varies depending on the previous state.

  For example, FIG. 6 shows a first conventional circuit example. In FIG. 6, the inverter has a first logic level determined by P-type MOSFET 601, P-type MOSFET 603 and N-type MOSFET 602, and a second logic level determined by N-type MOSFET 602, N-type MOSFET 604 and P-type MOSFET 601. The circuit 607, the P-type MOSFET 605, and the N-type MOSFET 606 generate hysteresis characteristics by properly using the first logic level and the second logic level described above depending on the previous state.

  FIG. 7 shows a second conventional circuit example, which is shown in Patent Document 1. In FIG. 7, a first logic level determined by P-type MOSFETs 701, 703, 705 and N-type MOSFETs 702, 704, and a second logic level determined by N-type MOSFETs 702, 704, 706 and P-type MOSFETs 701, 703 are shown. With the inverter circuit 707, the P-type MOSFET 705, and the N-type MOSFET 706, the first logic level and the second logic level described above are selectively used according to the previous state to create a hysteresis characteristic.

  FIG. 8 shows a third conventional circuit example, which is shown in Patent Document 2. In FIG. 8, the first logic level determined by the P-type MOSFETs 801, 803 and 805 and the N-type MOSFETs 802 and 804, and the second logic level determined by the N-type MOSFETs 802, 804 and 806 and the P-type MOSFETs 801 and 803, With the inverter circuit 807, the P-type MOSFET 805, and the N-type MOSFET 806, the first logic level and the second logic level described above are selectively used according to the previous state to create a hysteresis characteristic.

  FIG. 9 shows a fourth conventional circuit example, which is shown in Patent Document 3. 9 includes a first logic level determined by the P-type MOSFETs 911 and 915 and the N-type MOSFET 912, and a second logic level determined by the N-type MOSFETs 914 and 916 and the P-type MOSFET 913. The latch circuit 924, the P-type MOSFET 915, and the N-type MOSFET 916, which are configured by the circuit 921 and the inverter circuit 919, use the first logic level and the second logic level, depending on the previous state, to create hysteresis characteristics. It was.

  FIG. 10 shows a fifth conventional circuit example, which is shown in Patent Document 4. 10 includes a first logic level determined by the P-type MOSFET 1011 and the N-type MOSFETs 1012 and 1016, and a second logic level determined by the N-type MOSFET 1014 and the P-type MOSFETs 1013 and 1015. The latch circuit 1024 configured by the circuit 1021 and the inverter circuit 1019, the P-type MOSFET 1015, and the N-type MOSFET 1016 use the first logic level and the second logic level, depending on the previous state, to create hysteresis characteristics. It was.

JP 58-182914 A Japanese Patent Laid-Open No. 10-154924 Japanese Patent Laid-Open No. 11-27114 JP-A-2005-260601

  However, the conventional hysteresis input circuit has the following problems. 6, 7, and 8, which are input circuits having the above-described conventional hysteresis, are all formed of P-type MOSFETs and N-type MOSFETs as equivalent circuits when forming the first and second logic levels. In the end, this results in an inverter circuit. Note that the reason why the circuits of FIGS. 6, 7, and 8 result in the inverter circuit when the logic level is considered is that the signal of the input terminal is connected to the gate electrode in the combination of MOSFETs that are fundamental in determining the logic level. This is because the MOSFET is always included in the path. Therefore, although the equivalent β varies depending on whether the MOSFETs having the respective circuit configurations in FIGS. 6, 7, and 8 are in series or in parallel, they are equivalently converted into one P-type MOSFET and one N-type MOSFET.

As shown in FIG. 5, the logic level of the inverter circuit is such that the conductance constants of the P-type MOSFET and the N-type MOSFET are β _P and β _N , respectively, and the threshold voltages are V _TP and V _TN , respectively. If the power supply voltage is V _DD , the reference ground potential is 0, and the logic level is V _GL , then
(1/2) · β _P (V _DD −V _GL −V _TP ) ² = (1/2) · β _N (V _GL −V _TN ) ²
By solving this, the lock level V _GL becomes V _GL = {V _DD −V _TP + (β _N / β _P ) ^1/2 · V _TN } / {1+ (β _N / β _P ) ^{1 / 2} }
It becomes. Accordingly, if the P-type MOSFET and the N-type MOSFET are variously shaped and the conductance constant ratio (β _N / β _P ) is changed from 0 to infinity, the logic level changes within the following range.

V _TN <V _GL <V _DD -V _TP
At this time, when the higher logic level V _GLH is (β _N / β _P ) is 0, V _GLH = V _DD −V _TP
The lower logic level V _GLL is when (β _N / β _P ) is infinite, V _GLL = V _TN
It is. From these, the hysteresis width V _WHL is V _WHL = (V _GLH −V _GLL ) = V _DD −V _TP −V _TN
It becomes. However, since it is impossible to actually set (β _N / β _P ) to 0 or infinity, the hysteresis width is actually smaller than this. Accordingly, when the power supply voltage V _DD becomes a low voltage, for example, about 1.5 V, V _TP and V _TN are about 0.5 V to 0.7 V, so the hysteresis width becomes very small and the original purpose is not fulfilled. This is shown in FIG. In FIG. 4, when the input signal voltage is V _IN , the N-type MOSFET does not operate when 0 ≦ V _IN ≦ V _TN , and the P-type MOSFET does not operate when V _DD −V _TP ≦ V _IN ≦ V _DD . The logic level of the inverter circuit is limited to the range of V _TN <V _GL <V _DD −V _TP . Since the threshold voltages V _TP and V _TN do not fluctuate during operation, the logic level range (V _DD -V _TP -V _TN ) is narrowed when the power supply voltage V _DD is reduced, and the hysteresis width becomes very large as the power supply voltage decreases. Get smaller.

  Therefore, the hysteresis input circuit in which the conventional equivalent circuits as shown in FIGS. 6, 7 and 8 are connected to the inverter circuit has a problem that the hysteresis width cannot be sufficiently obtained when the voltage becomes low.

In addition, when trying to set (β _N / β _P ) in order to secure a little hysteresis width at the time of low voltage operation, it is necessary to change the shape of the P-type MOSFET or N-type MOSFET unnaturally. As a result, there are problems that it occupies a large chip area, or the driving ability is reduced to reduce the responsiveness.

In the fourth conventional example shown in FIG. 9, since the input terminal 910 is not connected to the gate electrodes of the P-type MOSFET 915 and the N-type MOSFET 916, the equivalent circuit of the inverter circuit of FIG. There are no logic level constraints. However, the first logic level is practically determined by the N-type MOSFET 912 and the P-type MOSFET 915 under the design conditions in which it is desired to ensure the hysteresis width, and the following problems arise. In FIG. 9, the conductance constants of the P-type MOSFET 915 and the N-type MOSFET 912 are β _P and β _N , respectively, and the threshold voltages are V _TP and V _TN , respectively. If the power supply voltage V _DD , the reference ground potential is 0, and the logic level is V _GL , then approximately V _GL ≈ (V _DD −V _TP ) − (β _N / β _P ) ^1/2 · (V _DD -V _TN)
It becomes. Here, if the value of (β _P / β _N ) is changed from 0 to infinity, −∞ ≦ V _IL ≦ V _DD −V _TP
It can be set to a range exceeding the power supply potential. At this time, (β _N / β _P ) ^1/2 = (V _DD −V _TP ) / (V _DD −V _TN )
When set to V _GL ≒ 0
Thus, the lower limit of V _GL of the inverter circuit described above is wider than V _TN . However, at this time, as a condition for setting the second logic level V _GLL , the _ratio of (β _N / β _P ) ^1/2 and (V _DD −V _TP ) / (V _DD −V _TN ) is set. As a point, since the setting is different between properties such as P-type MOSFET and N-type MOSFET, it is somewhat impossible to extend the hysteresis to the limit when manufacturing variation is taken into consideration. Further, as is understood from the equation of −∞ ≦ V _GLL ≦ V _DD −V _TP , V _GLL is set too low so as to be understood from the expression, and when V _GLL becomes _less than 0 due to variation in mass production, the input terminal 910 However, there is a problem that even if the signal potential is shifted in the range of the power supply voltage, it remains latched and enters a locked state, which makes it impossible to recover the operation. Even when the first logic level V _{GLH is} set, if it is set too _hard to ensure the hysteresis width, V _GLH will exceed V _DD and it will remain locked and fall into the locked state, making it impossible to recover the operation. There was a problem that the risk of becoming. Further, although it is easy to ensure hysteresis at low voltage, there is a problem that a sufficient hysteresis width cannot be obtained when the power supply voltage is increased by setting circuit constants designed with emphasis on low voltage.

Further, in the fifth conventional example of FIG. 10, since the input terminal 1010 is not connected to the gate electrodes of the P-type MOSFET 1015 and the N-type MOSFET 1016, the inverter circuit of FIG. 5 is similar to the fourth embodiment of FIG. It is not an equivalent circuit, and there are no logic level restrictions in FIG. Also, unlike the fourth embodiment of FIG. 9, the first logic level is determined by the N-type MOSFET 1012 and the N-type MOSFET 1016, and the second logic level is determined by the P-type MOSFET 1013 and the P-type MOSFET 1015. Since it is determined between the same conductivity types, stable characteristics can be obtained in manufacturing. However, the connection on the power supply side of the P-type MOSFET 1015 is negative -V _SS , and the connection on the power supply side of the N-type MOSFET 1016 is positive + V _DD . That is, the connection to the power source is made not on the source electrode side of the MOSFET but on the drain side. Therefore, although the low voltage characteristic is improved from the first to third examples of the conventional example, it is not better than the fourth example of FIG. Therefore, when an operation at an ultra-low voltage is intended, it is insufficient to provide a sufficient hysteresis characteristic.

  Therefore, the present invention is to solve such problems, and to provide a hysteresis input circuit that has a relatively large hysteresis width and is resistant to noise at a low voltage corresponding to a state in which the battery is exhausted. .

  It is another object of the present invention to provide a circuit capable of realizing an input circuit having a relatively large hysteresis width with an appropriate chip area.

  It is another object of the present invention to provide a hysteresis input circuit that secures a large hysteresis width over a wide range at low voltage and high voltage and does not cause an inoperable situation due to manufacturing variations.

  In order to solve the above-described problems and achieve the object of the present invention, each invention is configured as follows.

That is, the first invention is a hysteresis input circuit of a semiconductor integrated circuit device using an insulated gate field effect transistor, and includes a first P type insulated gate field effect transistor having a source electrode connected to a positive power source + V _DD , A first N-type insulated gate field effect transistor having a source electrode connected to a negative power source -V _SS; and a second N-type insulated gate field effect transistor having a drain electrode connected to a positive power source + V _DD ; , A second P-type insulated gate field effect transistor whose drain electrode is connected to the negative power source −V _SS , and a third P-type insulated gate field effect transistor whose source electrode is connected to the positive power source + V _DD When the third N-type insulated gate field effect transistor, a built-in plurality of inverter circuits input a source electrode connected to the power supply -V _SS of the negative electrode And a delay circuit having a positive-phase first output terminal and a negative-phase second output terminal, wherein the first P-type insulated gate field-effect transistor and the first N-type insulated gate field-effect transistor Each gate electrode is connected to each other, and each drain electrode is also connected to each other to form an inverter circuit, and each gate of the second N-type insulated gate field effect transistor and the second P-type insulated gate field effect transistor The electrodes are connected to each other, and the source electrodes are also connected to each other and connected to the drain electrodes of the first P-type insulated gate field effect transistor and the first N-type insulated gate field effect transistor, The gate electrodes of the P-type insulated gate field effect transistor and the third N-type insulated gate field effect transistor are connected to each other, and the drain electrodes are also connected to each other. Connected to the drain electrodes of the first P-type insulated gate field effect transistor and the first N-type insulated gate field effect transistor, and the input terminal of the delay circuit is connected to the first P-type insulated gate The gate field effect transistor and the first N-type insulated gate field effect transistor are connected to drain electrodes of the first N-type insulated gate field effect transistor, and the positive-phase first output terminal is connected to the second N-type insulated gate field effect transistor and the second P-type transistor. Connected to each gate electrode of the p-type insulated gate field effect transistor, and the second output terminal having the opposite phase is connected to each of the third p-type insulated gate field effect transistor and the third n-type insulated gate field effect transistor. The first P-type insulation connected to the gate electrode, and the first output terminal or the second output terminal connected to the output terminal as the circuit of the present invention and connected to each other Each gate electrode of the gate field effect transistor and the first N-type insulated gate field effect transistor is connected to an input terminal as a circuit of the present invention.

  A second invention is the first invention, wherein a conductance constant β of the first N-type insulated gate field effect transistor is larger than a conductance constant β of the second N-type insulated gate field effect transistor, and The conductance constant β of one P-type insulated gate field effect transistor is larger than the conductance constant β of the second P-type insulated gate field effect transistor.

  A third invention is the first invention, wherein a conductance constant β of the second N-type insulated gate field effect transistor is larger than a conductance constant β of the third P-type insulated gate field effect transistor, and The conductance constant β of the second P-type insulated gate field effect transistor is larger than the conductance constant β of the third N-type insulated gate field effect transistor.

  In a fourth aspect based on the first aspect, the delay circuit comprises two or more inverter circuits connected in series, and the inverter circuit comprises a P-type insulated gate field effect transistor and an N-type insulated gate field effect. Type transistor.

According to the present invention having the above-described configuration, the inverter circuit is configured by the first N-type MOSFET and the first P-type MOSFET controlled by the input signal, and is controlled by the signal of the delay circuit reflecting the previous state. The higher logic level V _GLH is set by the second N-type MOSFET and the third P-type MOSFET. Further, an inverter circuit composed of a first P-type MOSFET and a first N-type MOSFET controlled by an input signal, a second P-type MOSFET controlled by a signal of a delay circuit reflecting the previous state, and a third The lower logic level V _GLL is set by the N-type MOSFET. Therefore, not only the (β _N / β _P ) ratio of the inverter circuit of the first P-type MOSFET and the first N-type MOSFET controlled by the input signal, but also only by the signal of the delay circuit reflecting the previous state. Since it is determined by the total effect with the β ratio of the MOSFET to be applied, the above-described limitation of the logic level of the inverter circuit is released, and the range in which the logic level can be set increases.

Also, the hysteresis characteristic width at a relatively high normal standard voltage is controlled by the inverter circuit of the first N-type MOSFET and the first P-type MOSFET and the signal of the delay circuit reflecting the previous state. A higher logic level V _GLH is set _{predominantly} by the second N-type MOSFET and is controlled by an input signal. The inverter circuit of the first P-type MOSFET and the first N-type MOSFET, and the previous state The lower logic level V _GLL can be set _{predominantly} by the second P-type MOSFET controlled by the signal of the delay circuit reflecting the above.

Further, the hysteresis characteristic width at a very low voltage corresponding to the state where the battery is exhausted is the inverter circuit of the first N-type MOSFET and the first P-type MOSFET controlled by the input signal, and the previous state. The higher logic level V _GLH is set dominantly by the third P-type MOSFET controlled by the signal of the delay circuit reflecting the first P-type MOSFET and the first N-type MOSFET controlled by the input signal. The lower logic level V _GLL can be set _{predominantly} by the inverter circuit with the type MOSFET and the third N type MOSFET controlled by the signal of the delay circuit reflecting the previous state.

  Therefore, the hysteresis characteristic width can be secured over a wide range even at a normal standard power supply voltage and at a very low power supply voltage corresponding to a state where the battery is exhausted.

In addition, since it is easy to set a logic level value without forcibly setting (β _N / β _P ) of the first and second inverter circuits to an extreme value, an extreme MOSFET shape is not necessary and appropriate. There is an effect that a circuit having a chip occupation area can be realized.

  In the present invention, the conductance constant β of the first N-type MOSFET is larger than the conductance constant β of the second N-type MOSFET, and the conductance constant β of the first P-type MOSFET is the same as that of the second P-type MOSFET. By setting it larger than the conductance constant β, it is possible to reliably set the logic level within the range of the power supply voltage, so that the lock state can be prevented from entering. Therefore, in the case of normal standard power supply voltage, when the voltage is very low, the main element for setting the logic level is the β ratio of the MOSFETs of the same type, that is, the shape ratio. Therefore, the design can be facilitated, and the influence of fluctuations and variations in the manufacturing process on the hysteresis characteristics can be reduced.

  In the present invention, the conductance constant β of the second N-type MOSFET is larger than the conductance constant β of the third P-type MOSFET, and the conductance constant β of the second P-type MOSFET is the conductance of the third N-type MOSFET. By setting it larger than the constant β, it is possible to determine the β ratio of the MOSFET by shelving the normal standard power supply voltage at the time of ultra low voltage, so it is possible to avoid setting an excessive shape ratio, The risk of falling into a latched state forever due to differences between the design and the actual process is eliminated, and sufficient hysteresis width is secured over a wide power supply voltage range at ultra-low voltage and normal standard power supply voltage. There is an effect that can be done.

  Further, since a delay circuit including a plurality of inverter circuits is used as a circuit reflecting the previous state, there is an effect that two control signals can be configured with a small number of elements and a layout area.

  As described above, the hysteresis input circuit with a large hysteresis width and noise resistance can be stabilized over a wide range of power supply voltages even at a very low power supply voltage, which corresponds to a state where the battery has been exhausted from the normal standard power supply voltage. Can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment of high hysteresis width input circuit of the present invention)
FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a high hysteresis width input circuit according to the present invention. Hereinafter, the circuit configuration, operation, and logic level in each case will be described in order.

(Circuit configuration)
In FIG. 1, the source electrode of the P-type MOSFET 1 is connected to the positive power source + V _DD, and the source electrode of the N-type MOSFET 2 is connected to the negative power source −V _SS . The gate electrodes of the P-type MOSFET 1 and the N-type MOSFET 2 are connected to each other, and the drain electrodes are also connected to each other to constitute an inverter circuit 12 indicated by a broken line.

  Further, the inverter circuit 7 and the inverter circuit 8 are connected in series to constitute a delay circuit 13 indicated by a broken line. The output terminal of the inverter circuit 8 is a first output terminal having a positive phase as a delay circuit, and the output terminal of the inverter circuit 7 is a second output terminal having a reverse phase as a delay circuit.

The drain electrode of the N-type MOSFET 3 is connected to the positive power source + V _DD , the source electrode is connected to the output terminal of the inverter circuit 12, and the gate electrode is the first output terminal of the positive phase of the delay circuit 13. Is connected to the output terminal.

The source electrode of the P-type MOSFET 5 is connected to the positive power supply + V _DD , the drain electrode is connected to the output terminal of the inverter circuit 12, and the gate electrode is the second output terminal of the reverse phase of the delay circuit 13. Is connected to the output terminal.

Further, the drain electrode of the P-type MOSFET 4 is connected to the negative power source −V _SS , the source electrode is connected to the output terminal of the inverter circuit 12, and the gate electrode is an inverter circuit that is the positive-phase first output terminal of the delay circuit 13. 8 output terminals.

Further, the source electrode of the N-type MOSFET 6 is connected to the negative power source −V _SS , the drain electrode is connected to the output terminal of the inverter circuit 12, and the gate electrode is an inverter circuit that is the second output terminal of the reverse phase of the delay circuit 13. 7 output terminals.

  The input terminal of the inverter circuit 12 is the input terminal 10 as the high hysteresis width input circuit of the present invention. The output terminal of the inverter circuit 8 which is the positive phase first output terminal of the delay circuit 13 is the output terminal 11 as the high hysteresis width input circuit of the present invention.

(Operation)
In FIG. 1, it is assumed that the input terminal 10 is initially at a low potential. At this time, the output terminal of the inverter circuit 8 which is the first output terminal of the positive phase of the delay circuit 13 has a high potential, and the output terminal of the inverter circuit 7 which is the second output terminal of the reverse phase has a low potential. At this time, the P-type MOSFET 5 is on (ON) and the N-type MOSFET 6 is off (OFF). Further, the N-type MOSFET 3 is turned on (ON) and the P-type MOSFET 4 is turned off (OFF).

  Next, when the signal potential of the input terminal 10 gradually increases, the N-type MOSFET 2 of the inverter circuit 12 is more strongly turned on, but both the N-type MOSFET 3 and the P-type MOSFET 5 are turned on, and each gate is turned on. Therefore, a sufficient potential is supplied, and the output of the inverter circuit 12 tries to maintain a high potential, thereby preventing a low potential. On the other hand, the P-type MOSFET 4 and the N-type MOSFET 6 are both inactive because they are off. Therefore, the output terminal of the inverter circuit 12 continues to maintain a high potential, and the output terminal of the inverter circuit 8 that is the first phase output terminal of the delay circuit 13 is the high potential and the inverter that is the second phase output terminal of the opposite phase. The situation that the output terminal of the circuit 7 is at a low potential does not change, and the N-type MOSFET 6 and the P-type MOSFET 4 are turned off (OFF), so that the output terminal of the inverter circuit 12 keeps a high potential.

  When the signal potential at the input terminal 10 further increases and the driving capability of the N-type MOSFET 2 in the inverter circuit 12 exceeds the total driving capability of the P-type MOSFET 1, the N-type MOSFET 3, and the P-type MOSFET 5, the inverter circuit 12 The output changes from a high potential to a low potential, and the input potential of the delay circuit 13 changes from a high potential to a low potential, so that the output terminal of the inverter circuit 8 which is the first phase output terminal of the delay circuit 13 has a low potential. And the output terminal of the inverter circuit 7 which is a 2nd output terminal of a reverse phase becomes a high potential. As a result, both the N-type MOSFET 3 and the P-type MOSFET 5 are turned off, and both the P-type MOSFET 4 and the N-type MOSFET 6 are turned on.

  As a result, the first logic level determined by the inverter circuit 12, the N-type MOSFET 3 and the P-type MOSFET 5 changes, and the second logic level determined by the inverter circuit 12, the P-type MOSFET 4 and the N-type MOSFET 6 also changes.

  Next, when the signal potential of the input terminal 10 gradually decreases, the P-type MOSFET 1 of the inverter circuit 12 is turned on more strongly, but both the P-type MOSFET 4 and the N-type MOSFET 6 are turned on, and each gate is turned on. Therefore, a sufficient potential is supplied, and the output of the inverter circuit 12 is prevented from becoming a high potential in an attempt to maintain a low potential. On the other hand, the N-type MOSFET 3 and the P-type MOSFET 5 are both inactive because they are off. Therefore, the output terminal of the inverter circuit 12 continues to maintain a low potential, and the output terminal of the inverter circuit 8 that is the first phase output terminal of the delay circuit 13 is the low potential and the inverter that is the second output terminal of the opposite phase. The situation that the output terminal of the circuit 7 is at a high potential remains the same, and the P-type MOSFET 5 and the N-type MOSFET 3 are off (OFF), so that the output terminal of the inverter circuit 12 continues to maintain a low potential.

  When the signal potential of the input terminal 10 further decreases and the driving capability of the P-type MOSFET 1 in the inverter circuit 12 exceeds the total driving capability of the N-type MOSFET 2, the P-type MOSFET 4, and the N-type MOSFET 6, the inverter circuit 12 The output changes from a low potential to a high potential, and the input potential of the delay circuit 13 changes from a low potential to a high potential, so that the output terminal of the inverter circuit 8 which is the first output terminal of the delay circuit 13 is a high potential. In addition, the output terminal of the inverter circuit 7 which is the second output terminal having the opposite phase has a low potential. As a result, both the P-type MOSFET 4 and the N-type MOSFET 6 are turned off, and both the N-type MOSFET 3 and the P-type MOSFET 5 are turned on.

  As a result, the first logic level determined by the inverter circuit 12, the N-type MOSFET 3 and the P-type MOSFET 5 changes again, and the second logic level determined by the inverter circuit 12, the P-type MOSFET 4 and the N-type MOSFET 6 also changes again.

  Differences due to ON / OFF of the N-type MOSFET 3, the P-type MOSFET 5, the P-type MOSFET 4, and the N-type MOSFET 6 are causes of hysteresis.

  Note that when the input signal of the delay circuit 13 becomes an intermediate potential, the output signal may output an intermediate potential instead of a complete low potential or high potential. Keep at high potential. Therefore, hysteresis characteristics can be generated at least transiently.

(About logic level)
The circuit of the present invention of FIG. 1 has various logic levels depending on the situation. The logic levels in each case will be described in order below.

(About the higher logic level V _GLH )
Now, the inverter circuit 12, N-type MOSFET 3 and P-type MOSFET 5 that determine the higher logic level will be described below.

The conductance constants of the P-type MOSFET 1 and the N-type MOSFET 2 of the inverter circuit 12 and the P-type MOSFET 5 and the N-type MOSFET 3 that generate hysteresis characteristics are β _P1 , β _N1 , β _PS1 , β _NS1 , and the respective threshold voltages are V _TP , V _TN , V _TP , V _TN , the positive power supply voltage is V _DD , and the negative power supply −V _SS is the reference ground potential 0. The higher logic level V _GLH having the hysteresis characteristic at this time is calculated as follows.

Now, V _GLH is applied to the gate electrodes of the P-type MOSFET 1 and the N-type MOSFET 2 forming the inverter circuit 12 at the logic level. Further, the gate electrode of the P-type MOSFET 5 is turned on with a low potential (0) applied, and the source electrode is turned on as V _DD . The gate electrode of the N-type MOSFET 3 is turned on by applying a high potential (V _DD ), and the source electrode becomes (1/2) · V _DD which is exactly half of the power supply voltage at the time of transition at the logic level. ing. Note that this assumption is not necessarily guaranteed in a static steady state, but may be established in a transient state where the input signal changes.

At this time, the logic level V _GLH by the four MOSFETs satisfies the following equation (1).
(1/2) ・ β _P1 (V _DD −V _GLH −V _TP ) ² + (1/2) ・ β _NS1 ((1/2) ・ V _DD −V _TN ) ² + (1/2) ・ β _PS1 (V _DD −V _TP ) ² = (1/2) · β _N1 (V _GLH −V _TN ) ² (1)
here,
β _PS1 ≪β _NS1 (2)
And | V _TP | ≈ | V _TN | (3)
As the power supply voltage is high enough
(1/2) ・ V _DD >> V _TN (4)
If
(1/2) · β _NS1 ((1/2) · V _DD- V _TN ) ² > (1/2) · β _PS1 (V _DD- V _TP ) ² (5)
Is possible.
In addition, the power supply voltage is sufficiently low
((1/2) · V _DD −V _TN ) ² << (V _DD −V _TP ) ² (6)
If,
(1/2) • β _NS1 ((1/2) • V _DD −V _TN ) ² <(1/2) • β _PS1 (V _DD −V _TP ) ² (7)
Is possible. That is, in the relationship between the P-type MOSFET 5 and the N-type MOSFET 3 that are controlled by the second output signal of the reverse phase of the delay circuit 13 and the first output signal of the positive phase, respectively, if the power supply voltage V _DD is relatively high (2) Based on the results of the formulas (3) and (3), the N-type MOSFET 3 becomes dominant from the result of the formula (5), and if the power supply voltage V _DD becomes sufficiently low, the conditions of the formulas (3) and (6) are satisfied. In addition, the P-type MOSFET 5 is set to be dominant from the result of the expression (7).

Here, for simplification, the case where the power supply voltage V _DD is relatively high and the N-type MOSFET 3 is dominant and the case where the power supply voltage V _DD is sufficiently low and the P-type MOSFET 5 is dominant are considered separately.

(V _GLH when power supply voltage V _DD is relatively high)
Consider a case where the power supply voltage V _DD that satisfies the equation (4) is relatively high. At this time, since the N-type MOSFET 3 becomes dominant in the relationship between the P-type MOSFET 5 and the N-type MOSFET 3, the relational expression of the expression (1) is approximated as the following expression (8).
(1/2) ・ β _P1 (V _DD −V _GLH −V _TP ) ² + (1/2) ・ β _NS1 ((1/2) ・ V _DD −V _TN ) ² ≒ (1/2) ・ β _N1 (V _GLH -V _TN ) ² (8)
Furthermore, the lock level V _GL (V _GLH ) is to _satisfy the following conditional expression (9) in order to ensure the hysteresis width which is the original purpose and from the viewpoint of easy understanding.
V _DD −V _TP <V _GLH <V _DD (9)
Considering the range where the above holds, the P-type MOSFET 1 enters the OFF region, and the equation (8) becomes the following equation (10).
(1/2) · β _NS1 ((1/2) · V _DD- V _TN ) ² ≒ (1/2) · β _N1 (V _GLH- V _TN ) ² (10)
When the above equation (10) is solved, the higher logic level is obtained, and the following equation (11) is obtained.
V _GLH ≒ V _TN + (β _NS1 / β _N1 ) ^1/2 · ((1/2) · V _DD- V _TN ) (11)

When the equation (11) is substituted into the conditional expression (9) and solved, the following conditional expression (12) and conditional expression (13) are obtained.
(V _DD −V _TP −V _TN ) ² / ((1/2) · V _DD −V _TN ) ² <(β _NS1 / β _N1 ) (12)
And,
(Β _NS1 / β _N1 ) <(V _DD −V _TN ) ² / ((1/2) · V _DD −V _TN ) ² (13)
Here, the relationship of the expression (12) (V _DD −V _TP −V _TN ) ² / ((1/2) · V _DD −V _TN ) ² <(β _NS1 / β _N1 )
Therefore, a large hysteresis width can be secured, and the following conditional expression (14)
(Β _NS1 / β _N1 ) <(V _DD −V _TN ) ² / ((1/2) · V _DD −V _TN ) ² (14)
Then, since the logic level V _{GLH falls} within the range of the power supply voltage V _DD , the operation cannot be recovered by being locked by the circuit of FIG.

If the right side of the inequality of conditional expression (14) is expressed as F14,
F14 = (V _DD −V _TN ) ² / ((1/2) · V _DD −V _TN ) ² (15)
Under realistic conditions of 0 <V _TN <(1/2) · V _DD ,
4 <F14 <∞ (16)
Takes a value in the range.

In addition, if the left side of the inequality of conditional expression (12) is expressed as F12,
F12 = (V _DD −V _TP −V _TN ) ² / ((1/2) · V _DD −V _TN ) ² (17)
Under the condition of 0 <V _TN <(1/2) · V _DD and 0 <V _TP <(1/2) · V _DD , 1 <F12 <4 (18)
It becomes the range.

From the above, when (β _NS1 / β _N1 ) is set to about 1 to 4, a hysteresis input circuit capable of taking the hysteresis width to the maximum is realized. If the hysteresis width is too large, the input signal will not swing to the power supply voltage and will not fall into the locked state. To give priority to safety over the hysteresis width, (β _NS1 / β _N1 ) It can also be understood that it is sufficient to set 1 to about 1 or less.

Setting (β _NS1 / β _N1 ) to about 1 to 4 or about 1 is a conductance constant ratio of the N-type MOSFET, that is, a shape ratio, and can be easily set. More specifically, if the channel lengths of the transistors of the N-type MOSFET 3 and the N-type MOSFET 2 are the same, the transistor width of the N-type MOSFET 3 may be set to the ratio of the transistor width of the N-type MOSFET 2.

(V _GLH when power supply voltage V _DD is relatively low)
Next, consider a case where the power supply voltage V _DD is sufficiently low so that the expression (6) is satisfied. _Rewriting equation (1) that satisfies the logic level V _GLH of the four MOSFETs,
(1/2) ・ β _P1 (V _DD −V _GLH −V _TP ) ² + (1/2) ・ β _NS1 ((1/2) ・ V _DD −V _TN ) ² + (1/2) ・ β _PS1 (V _DD −V _TP ) ² = (1/2) · β _N1 (V _GLH −V _TN ) ² (1)
Here, the power supply voltage V _DD becomes sufficiently low, that is,
((1/2) · V _DD −V _TN ) ² << (V _DD −V _TP ) ² (6)
Then,
β _PS1 ≪β _NS1 (2)
Even
(1/2) • β _NS1 ((1/2) • V _DD −V _TN ) ² <(1/2) • β _PS1 (V _DD −V _TP ) ² (21)
It becomes. Or it is possible to set in this way. That is, in the relationship between the P-type MOSFET 5 and the N-type MOSFET 3 controlled by the negative phase second output signal of the delay circuit 13 and the positive phase first output signal, respectively, the power supply voltage V _DD increases as the conditional expression (6) is satisfied. Is sufficiently low, the P-type MOSFET 5 becomes dominant from the result of the equation (21). Therefore, the relational expression (1) is approximated as the following expression (22).
(1/2) ・ β _P1 (V _DD −V _GLH −V _TP ) ² + (1/2) ・ β _PS1 (V _DD −V _TP ) ² ≒ (1/2) ・ β _N1 (V _GLH −V _TN ) ² ... (22)
Furthermore, the lock level V _GL (V _GLH ) is to _satisfy the following conditional expression (9) in order to ensure the hysteresis width which is the original purpose and from the viewpoint of easy understanding.
V _DD −V _TP <V _GLH <V _DD (9)
(22) is
(1/2) ・ β _PS1 (V _DD −V _TP ) ² ≒ (1/2) ・ β _N1 (V _GLH −V _TN ) ² (23)
And simplified
V _GLH ≒ V _TN + (β _PS1 / β _N1 ) ^1/2 · (V _DD- V _TP ) (24)
It becomes. Here, for example, when the value of (β _PS1 / β _N1 ) is changed from 0 to infinity, V _GLH becomes V _TN ≦ V _GLH ≦ ∞ (25) from the equation (24).
It becomes. That is, it can be understood that the value near the V _TN can be set up to a range exceeding the power supply voltage of the positive electrode. Further, at this time, (β _PS1 / β _N1 ) ^1/2 = (V _DD −V _TN ) / (V _DD −V _TP ) (26)
To set
V _GLH ≒ V _DD (27)
Thus, the higher logic level can be set up to the positive power supply voltage. This shows that the upper limit of the higher logic level resulting from the conventional inverter circuit is wider than (V _DD -V _TP ).

Now, the logic level V _GLH The higher the sufficiently high area so the power supply voltage V _DD is represented in equation (4), is expressed by equation (11), represented in the power supply voltage V _DD (6) In a sufficiently low region, it is expressed by the equation (24).

As seen from the equation (11), when the power supply voltage V _DD is high, the ratio of the same type of MOSFET is used, so that an easy and stable characteristic can be obtained in terms of design and manufacturing. However, when the power supply voltage V _DD becomes low Since the system relies on the N-type MOSFET 3 in which the power source is connected to a normal reverse potential, it does not function effectively.

On the other hand, in the equation (24), even if the power supply voltage V _DD is lowered, a good hysteresis characteristic can be obtained by using a method depending on the P-type MOSFET 5 in which a normal source is connected to the power supply. However, if β _PS1 , which is an index of the driving ability of the P-type MOSFET 5, is set large or set to the same level as β _N1 at this time, the higher logic level is understood from the relational expression (24). Since V _GLH exceeds the power supply voltage V _DD and once it functions, it will be locked forever. Therefore, it is necessary to set β _{PS1 of the} P-type MOSFET 5 small. Then, when the power supply voltage V _DD is high, the ratio of (β _PS1 / β _N1 ) is small, so that sufficient hysteresis characteristics cannot be obtained with the relational expression (24).

From the above, while the method dependent on the N-type MOSFET 3 has good characteristics on the high power supply voltage side, the characteristic on the low power supply voltage side is insufficient, and the method dependent on the P-type MOSFET 5 has characteristics on the low power supply voltage side. On the other hand, the characteristics on the high power supply voltage side are insufficient. Therefore, when the N-type MOSFET 3 and the P-type MOSFET 5 are combined as in the circuit of FIG. 1, it can be seen that the higher logic level V _GLH can obtain stable characteristics against a wide range of fluctuations in the power supply voltage.

(Lower logic level V _GLL )
Next, the lower logic level V _GLL will be described. It is mainly the inverter circuit 12, the P-type MOSFET 4, and the N-type MOSFET 6 that determine the lower logic level.

The conductance constants of the P-type MOSFET 1 and the N-type MOSFET 2 of the inverter circuit 12 and the P-type MOSFET 4 and the N-type MOSFET 6 that generate hysteresis characteristics are β _P1 , β _N1 , β _PS2 , β _NS2 , and the respective threshold voltages are V _TP , V _TN , V _TP , V _TN , the power supply voltage is V _DD , and the reference ground potential is 0. The lower logic level V _GLL in the logic level having the hysteresis characteristic at this time is calculated as follows.

Now, V _GLL is applied to the gate electrodes of the P-type MOSFET 1 and the N-type MOSFET 2 forming the inverter circuit 12 at the logic level. The gate electrode of the N-type MOSFET 6 is turned on with a high potential (V _DD ) applied thereto, and the source electrode is turned on with a zero potential. The gate electrode of the P-type MOSFET 4 is turned on with a low potential (0) applied, and the source electrode becomes (1/2) · V _DD which is exactly half of the power supply voltage at the time of transition at the logic level. Yes. At this time, the logic level V _GLL by the four MOSFETs satisfies the following equation (28).
(1/2) · β _N1 ( _{VGLL –} V _TN ) ² + (1/2) · β _PS2 ((1/2) · V _DD- V _TP ) ² + (1/2) · β _NS2 (V _DD −V _TN ) ² = (1/2) · β _P1 (V _DD −V _GLL −V _TP ) ² (28)
here,
β _NS2 ≪β _PS2 (29)
And | V _TP | ≈ | V _TN | (3)
As
(1/2) ・ V _DD ≫V _TP・ ・ ・ （30）
If
(1/2) · β _PS2 ((1/2) · V _DD- V _TP ) ² > (1/2) · β _NS2 (V _DD- V _TN ) ² (31)
Is possible.
In addition, the power supply voltage is sufficiently low
((1/2) · V _DD −V _TP ) ² << (V _DD −V _TN ) ² (32)
If,
(1/2) · β _PS2 ((1/2) · V _DD- V _TP ) ² <(1/2) · β _NS2 (V _DD- V _TN ) ² ... (33)
It becomes. That is, in the relationship between the N-type MOSFET 6 and the P-type MOSFET 4 controlled by the first output signal having the positive phase and the second output signal having the opposite phase, respectively, the power supply voltage V _DD is relatively high (29 ) And (3), the P-type MOSFET 4 becomes dominant from the result of the equation (31), and the power supply voltage V _DD becomes sufficiently low, the conditions of the equations (3) and (32) are satisfied. Based on the result of the equation (33), the N-type MOSFET 6 becomes dominant.

Here, for simplification, the case where the power supply voltage V _DD is relatively high and the P-type MOSFET 4 becomes dominant and the case where the power supply voltage V _DD is sufficiently low and the N-type MOSFET 6 becomes dominant are considered separately.

(V _GLL when power supply voltage V _DD is relatively high)
Next, let us consider a case where the power supply voltage V _DD that satisfies the expression (30) is relatively high. At this time, since the P-type MOSFET 4 is dominant in the relationship between the N-type MOSFET 6 and the P-type MOSFET 4, the relational expression of the expression (28) is approximated as the following expression (34).
(1/2) · β _N1 ( _{VGLL –} V _TN ) ² + (1/2) · β _PS2 ((1/2) · V _DD- V _TN ) ² ≒ (1/2) · β _P1 (V _DD -V _GLL -V _TP ) ² ... (34)
Furthermore, the logic level V _GL (V _GLL ) is to _satisfy the following conditional expression (35) in order to ensure the hysteresis width which is the original purpose and from the viewpoint of easy understanding.
0 <V _GLL <V _TN (35)
Then, the N-type MOSFET 2 enters the OFF region, and the equation (34) is
(1/2) · β _PS2 ((1/2) · V _DD- V _TN ) ² ≒ (1/2) · β _P1 (V _DD- V _GLL- V _TP ) ² ... (36)
It becomes. When this equation (36) is solved, the lower logic level is obtained, and the following equation (37) is obtained.
V _GLL ≒ (V _DD- V _TP )-(β _PS2 / β _P1 ) ^1/2 · ((1/2) · V _DD- V _TP ) (37)

When the equation (37) is substituted into the conditional expression (35) and solved, the following conditional expression (38) and conditional expression (39) are obtained.
(V _DD −V _TP −V _TN ) ² / ((1/2) · V _DD −V _TP ) ² <(β _PS2 / β _P1 ) (38)
And,
(Β _PS2 / β _P1 ) <(V _DD −V _TP ) ² / ((1/2) · V _DD −V _TP ) ² (39)
Here, the relationship of the equation (38) (V _DD −V _TP −V _TN ) ² / ((1/2) · V _DD −V _TP ) ² <(β _PS2 / β _P1 )
Therefore, a large hysteresis width can be secured, and the following conditional expression (40)
(Β _PS2 / β _P1 ) <(V _DD −V _TP ) ² / ((1/2) · V _DD −V _TP ) ² (40)
Then, since the logic level V _{GLL falls} within the range of the power supply voltage 0, the operation cannot be recovered from being locked by the circuit of FIG.

Moreover, if the right side of the inequality of the conditional expression (39) is expressed as F39,
F39 = (V _DD −V _TP ) ² / ((1/2) · V _DD −V _TP ) ² (41)
Is between 0 <V _TP <(1/2) · V _DD
4 <F39 <∞ (42)
The value of the range.

Also, if the left side of the inequality of conditional expression (38) is expressed as F38,
F38 = (V _DD −V _TP −V _TN ) ² / ((1/2) · V _DD −V _TP ) ² (43)
_Are realistic 0 <V _TP <(1/2) · V _DD and 0 <V _TN <(1/2) · V _DD (44)
1 <F38 <4 (45)
It becomes the range.

From the above, if (β _PS2 / β _P1 ) is set to about 1 to 4, a hysteresis input circuit capable of taking the hysteresis width to the maximum is realized. In addition, if the hysteresis width is too large, the input signal will not swing to the power supply voltage, and in order to avoid falling into the locked state, when safety is prioritized over the hysteresis width, set (β _PS2 / β _P1 ). It can also be seen that it may be set to about 1 or less.

Setting (β _PS2 / β _P1 ) to about 1 to 4 or about 1 is a conductance constant ratio of the P-type MOSFET, that is, a shape ratio, and can be easily set. More specifically, if the channel lengths of the transistors of the P-type MOSFET 4 and the P-type MOSFET 1 are the same, the transistor width of the P-type MOSFET 4 may be set to the ratio of the transistor width of the P-type MOSFET 1.

(V _GLL when power supply voltage V _DD is relatively low)
Next, consider a case where the power supply voltage V _DD is sufficiently low so as to satisfy the equation (32). _Rewriting equation (28) that satisfies the logic level V _GLH of the four MOSFETs,
(1/2) · β _N1 ( _{VGLL –} V _TN ) ² + (1/2) · β _PS2 ((1/2) · V _DD- V _TP ) ² + (1/2) · β _NS2 (V _DD −V _TN ) ² = (1/2) · β _P1 (V _DD −V _GLL −V _TP ) ² (28)
Here, the power supply voltage V _DD becomes sufficiently low, that is,
((1/2) · V _DD −V _TP ) ² << (V _DD −V _TN ) ² (32)
Then,
β _NS2 ≪β _PS2 (29)
Even
(1/2) · β _PS2 ((1/2) · V _DD- V _TP ) ² <(1/2) · β _NS2 (V _DD- V _TN ) ² ... (46)
It becomes. That is, in the relationship between the N-type MOSFET 6 and the P-type MOSFET 4 that are controlled by the first output signal having the positive phase and the second output signal having the opposite phase, respectively, the power supply voltage V is increased to satisfy the conditional expression (32). _{If DD} becomes sufficiently low, the N-type MOSFET 6 becomes dominant from the result of the equation (46). Therefore, the relational expression of the expression (28) is approximated as the following expression (47).
(1/2) • β _N1 (V _GLL −V _TN ) ² + (1/2) • β _NS2 (V _DD −V _TN ) ² ≒ (1/2) • β _P1 (V _DD −V _GLL −V _TP ) ² ... (47)
Here, the following assumptions of the following equations (32) and (35):
0 <V _GLL <V _TN (35)
(47) is
(1/2) ・ β _NS2 (V _DD −V _TN ) ² ≒ (1/2) ・ β _P1 (V _DD −V _GLL −V _TP ) ²・ ・ ・ (48)
And simplified
V _GLL ≈V _DD −V _TP − (β _NS2 / β _P1 ) ^1/2 · (V _DD −V _TN ) (49)
It becomes. Here, for example, when the value of (β _NS2 / β _P1 ) is changed from 0 to infinity, V _GLL is _expressed as −∞ ≦ V _GLL ≦ V _DD −V _TP (50) from the equation (49).
It becomes. That is, it can be understood that the value in the vicinity of (V _DD −V _TP ) can be set up to a range exceeding the power supply voltage of the negative electrode. Further, at this time, (β _NS2 / β _P1 ) ^1/2 = (V _DD −V _TP ) / (V _DD −V _TN ) (51)
To set
V _GLL ≒ 0 ... (52)
Thus, the lower logic level can be set up to the negative power supply voltage. It can be seen that this is widened compared to the lower limit of the higher logic level that results in the conventional inverter circuit only up to V _TN .

In the _{region where} the lower logic level V _GLL is sufficiently high so that the power supply voltage V _DD is expressed by the equation (30), the logic level V _GLL is expressed by the equation (37), and the power supply voltage V _DD is (32). The logic level V _GLL is expressed by the equation (49) in a sufficiently low region as expressed by the equation (49).

As seen from the equation (37), when the power supply voltage V _DD is high, the ratio of the same type of MOSFET is used, so that an easy and stable characteristic can be obtained in terms of design and manufacture. However, when the power supply voltage V _DD becomes low Since the system relies on the P-type MOSFET 4 in which the power source is connected to a normal reverse potential, it does not function effectively.

On the other hand, looking at the equation (49), even if the power supply voltage V _DD is lowered, a good hysteresis characteristic can be obtained by using a method depending on the N-type MOSFET 6 in which a normal source is connected to the power supply. However, if β _NS2 , which is an index of the driving capability of the N-type MOSFET 6, is set large or set to the same level as β _P1 at this time, the lower logic level as understood from the relational expression (49). Since V _GLL drops beyond the power supply voltage 0, and once it functions, it will be locked forever. Therefore, it is necessary to set β _{NS2 of the} N-type MOSFET 6 small. Then, when the power supply voltage V _DD is high, since the (β _NS2 / β _P1 ) ratio is small, sufficient hysteresis characteristics cannot be obtained with the relational expression (49).

From the above, while the method depending on the P-type MOSFET 4 has good characteristics on the high power supply voltage side, the characteristic on the low power supply voltage side is insufficient, and the method dependent on the N-type MOSFET 6 has characteristics on the low power supply voltage side. On the other hand, the characteristics on the high power supply voltage side are insufficient. Therefore, when the P-type MOSFET 4 and the N-type MOSFET 6 are combined as shown in FIG. 1, it can be seen that the higher logic level V _GLL can obtain stable characteristics against a wide range of fluctuations in the power supply voltage.

  The setting of the conductance constant β ratio between the N-type MOSFETs 2 and 3 and the P-type MOSFETs 1 and 5 and the setting of the conductance constant β ratio between the P-type MOSFETs 1 and 4 and the N-type MOSFETs 2 and 6 are within a reasonable range. There is no need to use an extremely large value or a small value as in the prior art. Therefore, since it is natural in designing the layout pattern, it can be understood that problems such as an increase in chip area and a decrease in responsiveness are not caused.

From the above, if the conductance constant β _N1 of the N-type MOSFET 2 is set larger than the conductance constant β _NS1 of the N-type MOSFET 3, and the conductance constant β _P1 of the P-type MOSFET 1 is set larger than the conductance constant β _PS2 of the P-type MOSFET 4. The risk of falling into a locked state can be further avoided.

If the conductance constant β _NS1 of the N-type MOSFET 3 is set larger than the conductance constant β _PS1 of the P-type MOSFET 5 and the conductance constant β _PS2 of the P-type MOSFET 4 is set larger than the conductance constant β _NS2 of the N-type MOSFET 6, the locked state is established. The hysteresis width can be stably secured in a wide power supply voltage range from low voltage to high voltage.

Incidentally, the V _GLL is lower than V _TN, also illustrating how V _GLH is having a value higher than (V _DD -V _TP) by more than a 3. In FIG. 3, it can be seen that a large hysteresis width is secured from the characteristic diagram 4 of the system resulting from the conventional inverter.

(Other embodiments)
The present invention is not limited to the above-described embodiments. For example, in FIG. 1, the delay circuit 13 is configured by connecting two inverter circuits 7 and 8 in series. However, this is merely an example, and three inverter circuits 7 and 8 are provided as shown in FIG. , 9 may be connected in series. At this time, the positive-phase first output terminal is the output terminal of the inverter circuit 8, and the negative-phase second output terminal is the output terminal of the inverter circuit 9. Thus, the delay circuit 14 constituted by three inverter circuits increases the delay time from the input signal to the output signal by the increase in the number of inverter stages, and increases the allowable time in which the hysteresis characteristic in the transient state appears. effective.

  Further, the number of inverter circuits in the delay circuit may be four or more.

  Further, although the method of setting the MOSFET conductance constant β ratio included in each conditional expression by changing the channel width of the MOSFET transistor has been described, a method of changing the channel length of the transistor may be used. If the channel width is increased, β increases, but if the channel length is increased, β decreases.

  Although the main setting was made to increase the hysteresis width, if the hysteresis width is not required until the above method is obtained, or if a logic level exceeding the power supply voltage is set, the above conditional expression is used. It is not always necessary to be concerned. Even in that case, the circuit according to the present invention of FIG. 1 makes it easy to set the β ratio of the MOSFET, and is effective in applying an effective layout pattern design and ensuring response speed.

1 is a circuit diagram showing a first embodiment of a high hysteresis width input circuit of the present invention. The circuit diagram which shows 2nd Embodiment of the high hysteresis width input circuit of this invention. The electrical characteristic figure which illustrated the example of the hysteresis characteristic of the high hysteresis width input circuit of this invention. The electrical characteristic figure which illustrated the hysteresis characteristic example of the conventional hysteresis input circuit. The circuit diagram which shows the structure of the inverter circuit used in the circuit of this invention, and a conventional circuit. The circuit diagram which shows the 1st example of the conventional hysteresis input circuit. The circuit diagram which shows the 2nd example of the conventional hysteresis input circuit. The circuit diagram which shows the 3rd example of the conventional hysteresis input circuit. The circuit diagram which shows the 4th example of the conventional hysteresis input circuit. The circuit diagram which shows the 5th example of the conventional hysteresis input circuit.

Explanation of symbols

  1, 4, 5, 501, 601, 603, 605, 701, 703, 705, 801, 803, 805, 911, 913, 915, 1011, 1013, 1015... P-type MOSFET, 2, 3, 6, 502, 602, 604, 606, 702, 704, 806, 802, 806, 912, 914, 916, 1012, 1014, 1016 ... N-type MOSFET, 920, 921, 1020, 1021 ... NAND circuit, 7, 8, 9 , 12, 607, 707, 807, 919, 1019 ... inverter circuit, 10, 510, 610, 710, 810, 910, 1010 ... input terminal, 11, 511, 611, 711, 811, 925, 1026 ... output terminal, 13, 14 ... delay circuits.

Claims (4)

In a hysteresis input circuit of a semiconductor integrated circuit device using an insulated gate field effect transistor,
A first P-type insulated gate field effect transistor having a source electrode connected to a positive power supply + V _DD ;
A first N-type insulated gate field effect transistor having a source electrode connected to a negative power source -V _SS ;
A second N-type insulated gate field effect transistor having a drain electrode connected to a positive power supply + V _DD ;
A second P-type insulated gate field effect transistor having a drain electrode connected to the negative power source -V _SS ;
A third P-type insulated gate field effect transistor whose source electrode is connected to the positive power supply + V _DD ;
A third N-type insulated gate field effect transistor having a source electrode connected to a negative power supply −V _SS ;
A delay circuit including a plurality of inverter circuits, having an input terminal, a first output terminal having a positive phase, and a second output terminal having a reverse phase;
The gate electrodes of the first P-type insulated gate field effect transistor and the first N-type insulated gate field effect transistor are connected to each other, and the drain electrodes are also connected to each other to form an inverter circuit.
The gate electrodes of the second N-type insulated gate field effect transistor and the second P-type insulated gate field effect transistor are connected to each other, and the source electrodes are also connected to each other to connect the first P-type insulated gate. Connected to the drain electrode of the field effect transistor and the first N-type insulated gate field effect transistor;
The gate electrodes of the third P-type insulated gate field effect transistor and the third N-type insulated gate field effect transistor are connected to each other, and the drain electrodes are also connected to each other. Connected to the drain electrode of the field effect transistor and the first N-type insulated gate field effect transistor;
The input terminal of the delay circuit is connected to the drain electrodes of the first P-type insulated gate field effect transistor and the first N-type insulated gate field effect transistor, and the positive-phase first output terminal is the second output terminal. The N-type insulated gate field effect transistor and the second P-type insulated gate field effect transistor are connected to gate electrodes of the second P-type insulated gate field effect transistor, and the second output terminal having the opposite phase is connected to the third P-type insulated gate field effect transistor. And a third N-type insulated gate field effect transistor, and the first output terminal or the second output terminal is connected to an output terminal as a circuit of the present invention,
Each gate electrode of the first P-type insulated gate field effect transistor and the first N-type insulated gate field effect transistor connected to each other is connected to an input terminal as a circuit of the present invention. High hysteresis width input circuit.   In the first and second N-type insulated gate field effect transistors and the first and second P-type insulated gate field effect transistors, the conductance constant β of the first N-type insulated gate field effect transistor is 2 is larger than the conductance constant β of the N-type insulated gate field effect transistor, and the conductance constant β of the first P-type insulated gate field effect transistor is larger than the conductance constant β of the second P-type insulated gate field effect transistor. 2. The high hysteresis width input circuit according to claim 1, wherein the high hysteresis width input circuit is large.   The second N-type insulated gate field effect transistor and the third P-type insulated gate field effect transistor, and the second P-type insulated gate field effect transistor and the third N-type insulated gate field effect transistor. In the type transistor, the conductance constant β of the second N-type insulated gate field effect type is larger than the conductance constant β of the third P-type insulated gate field effect type and the conductance constant of the second P-type insulated gate field effect type 2. The high hysteresis width input circuit according to claim 1, wherein β is larger than a conductance constant β of the third N-type insulated gate field effect type.   The delay circuit includes two or three or more inverter circuits connected in series, and the inverter circuit includes a P-type insulated gate field effect transistor and an N-type insulated gate field effect transistor. The high hysteresis width input circuit according to claim 1.

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