JPH10117138A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the semiconductor integrated circuit that enhances its capability independently of a power supply voltage and is manufactured at a low cost. SOLUTION: A power supply voltage detection circuit provided to the semiconductor integrated circuit provides an output of a high level signal from its node S1 when a power supply voltage of the IC is lower than a prescribed voltage and provides an output of a low level signal from its node S1 when the power supply voltage of the IC is higher than the prescribed voltage. Then the output signal of the node S1 is used for a control signal to select the number of stages of a timing compensation delay circuit that makes a drive sequence of each circuit in the semiconductor integrated circuit proper thereby realizing the semiconductor integrated circuit that fulfills a prescribed function over a wide operating power supply voltage range and is manufactured at a low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit operable with a wide range of power supply voltages.

[0002]

2. Description of the Related Art At present, many ICs (integrated circuits) on the market have a recommended power supply voltage of 5V. However, depending on the application, an IC that can be used with a power supply voltage lower than 5 V is required. For example, when an IC is mounted on a device using a battery as a power supply, a power supply voltage of the IC is desired to be about 3.3 V.

However, each element of the IC has a power supply voltage of 5
When the power supply voltage is 5 V
If it is lower than a certain level, the electrical characteristics of each element greatly change, and the desired function of the IC may not be exhibited. For example, MOSFET (metal-oxide film-
The drive capability of a field effect transistor having a semiconductor structure) decreases as the power supply voltage decreases, and it becomes impossible to supply a sufficient drive current to a load. For this reason, the operation of each element in the semiconductor integrated circuit is significantly delayed, and the electrical performance of the IC is significantly deteriorated. In particular, in the case of an analog circuit, in many cases, the intended function cannot be performed at all because the current flowing through the MOSFET decreases. Therefore, conventionally, I
When the range of the power supply voltage required by C is wide, ICs suitable for each power supply voltage have been separately manufactured.

[0004]

For this reason, a plurality of types of power supply voltages within the range are assumed in consideration of the range of the power supply voltage used by each user, in spite of the fact that the conventional functions are the same. Since the ICs were separately manufactured, there was a problem that the manufacturing cost increased. Further, when an optimum circuit configuration (for example, transistor size, etc.) for exhibiting a desired function (for example, a plurality of circuits each having a different drive timing is driven at a desired timing) differs depending on a used power supply voltage. However, in such a case, an IC having the same function cannot be dealt with by changing the manufacturing conditions or the like.
However, it is necessary to change the circuit configuration depending on the power supply voltage used. Therefore, in order to manufacture each IC corresponding to each power supply voltage to be used, different masks must be prepared, and there is a problem that the manufacturing cost is further increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a semiconductor integrated circuit which can exhibit desired capabilities irrespective of power supply voltage and can be manufactured at low cost. With the goal.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a semiconductor integrated circuit having a plurality of circuits with different driving timings, a voltage dividing circuit for dividing a power supply voltage and outputting the same, and a reference voltage generating circuit for outputting a reference voltage. And a comparison circuit that compares the output voltage of the voltage dividing circuit with the reference voltage and outputs the comparison result as a control signal, and a delay circuit having a plurality of stages, and the control signal determines the number of stages of the delay circuit. A timing compensating circuit for switching and compensating drive timings of the plurality of circuits.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Such an embodiment shows one aspect of the present invention, and does not limit the present invention in any way, and can be arbitrarily changed within the scope of the present invention. FIG. 1 is a circuit diagram showing a configuration of a power supply voltage detection circuit provided in a semiconductor integrated circuit according to an embodiment of the present invention. The power supply voltage detection circuit detects a power supply voltage of the IC, and is formed on a semiconductor chip together with a circuit for realizing the function of the IC.

In FIG. 1, reference numeral 2 denotes a voltage dividing circuit, which includes P-channel MOSFETs 21 to 23 and an N-channel MOSFET.
T24 and T25 are connected in series between the power supply and ground of the IC. P-channel MOSFETs 21 to 23 and N
The drains and the gates of the channel MOSFETs 24 and 25 are commonly connected, and both MOSFETs are turned on when a power supply voltage is applied to the IC. With such a configuration, the P-channel MOSFE
From the node S2 where the drain of T23 and the drain of the N-channel MOSFET 24 are connected, a voltage obtained by dividing the power supply voltage VDD by a predetermined voltage dividing ratio is obtained.

The reference voltage generating circuit 3 is a P-channel MOS
The FET 31 and N-channel MOSFETs 32 and 33 are sequentially connected in series between a power supply and a ground. The source of the P-channel MOSFET 31 is connected to the power supply terminal. When the power supply voltage detection circuit is operated, a low-level voltage is applied to the gate of the P-channel MOSFET 31 and the P-channel MOSFET 31 is turned on. The N-channel MOSFET 32 is a depletion-type FET having a negative gate threshold voltage, and the drain is a P-channel MOSFET.
The drain and gate of the SFET 31 are connected to the drain of the N-channel MOSFET 33.

As described above, the N-channel MOSFET 32
Has a voltage between the gate and the source fixed at 0 V, and the difference between the voltage between the gate and the source (0 V) and the gate threshold voltage (<0 V) becomes a net gate bias, so that the voltage between the source and the drain is reduced. An inversion layer is formed. Therefore, in the N-channel MOSFET 32, a substantially constant drain current always flows even if the voltage between the drain and the source changes due to a change in the power supply voltage VDD.

The N-channel MOSFET 33 has a source grounded and a drain and gate N-channel MOSFET.
The source and the gate of the OSFET 32 are commonly connected. Then, the N-channel MOSFET 32
Supplied through the N-channel MOSFET 33
Flows as a drain current. As described above, the magnitude of the drain current of the N-channel MOSFET 32 is equal to the power supply voltage V
Since it is almost constant irrespective of the DD, the N-channel MOSF
The drain voltage of the ET 33, that is, the voltage of the node S3 in FIG. 1 also becomes substantially constant regardless of the power supply voltage VDD.

Reference numeral 4 denotes a reference voltage generation circuit having the same structure as the reference voltage generation circuit 3;
An ET 41 and N-channel MOSFETs 42 and 43 output a substantially constant voltage from the node S4 regardless of the power supply voltage VDD.

The comparison circuit 1 includes a P-channel MOSFET 1
1 to 13 and N-channel MOSFETs 14 to 16. The source of the P-channel MOSFET 11 is connected to the power supply terminal. When the power supply voltage detection circuit is operated, a low-level voltage is applied to the gate of the P-channel MOSFET 11 and the P-channel MOSFET 11 is turned on. The sources of the P-channel MOSFETs 12 and 13 are commonly connected to the drains of the P-channel MOSFET 11, and the respective drains are connected to the drains of the N-channel MOSFETs 15 and 16.

Further, these P-channel MOSFETs 1
2 and 13 are P-channel MOSFETs 13
And the drain of the N-channel MOSFET 16 is connected in common. N-channel MOSFE
Each gate of T15 and T16 is connected to the node S of the voltage dividing circuit 2.
2 and the node S3 of the reference voltage generating circuit 3. Also, N-channel MOSFETs 15 and 1
6 are commonly connected to the drain of the N-channel MOSFET 14. This N-channel MOSFET 1
4 has a source grounded and a gate connected to the node S4 of the reference voltage generation circuit 4.

FIG. 2 shows a simulation result of a change in the voltage of each of the nodes S1 to S4 when the power supply voltage VDD is gradually increased from 0V. Hereinafter, referring to this figure,
The operation of the power supply voltage detection circuit will be described.

First, the output voltage at the node S2 of the voltage dividing circuit 2 is substantially proportional to the power supply voltage VDD as shown in FIG. On the other hand, the output voltage of the node S3 of the reference voltage generation circuit 3 changes as follows with respect to the power supply voltage VDD. First, when the power supply voltage VDD is equal to or lower than the gate threshold voltage of the P-channel MOSFET 31, the P-channel MOS
Since the FET 31 is off, the N-channel MOSFE
No drain current flows through T33, and the output voltage of the node S3 becomes 0V.

When the power supply voltage VDD is a P-channel MOSFE
When the voltage exceeds the gate threshold voltage of T31, the P-channel MOSFET 31 is turned on, so that a drain current flows through the N-channel MOSFET 33 and the node S3
Output voltage rises sharply. However, thereafter, as described above, since the drain current of the depletion-mode MOSFET 32 becomes substantially constant irrespective of the power supply voltage VDD, the output voltage of the node S3 tends to be saturated with an increase in the power supply voltage VDD. The node S4 of the reference voltage generation circuit 4 changes in exactly the same manner as the node S3.

When power supply voltage VDD is lower than a predetermined value and the output voltage of node S2 of voltage dividing circuit 2 is lower than the output voltage of node S3 of reference voltage generating circuit 3, N channel M
N-channel MOS compared to the gate voltage of OSFET16
The gate voltage of the FET 15 becomes insufficient. Therefore, the output voltage of the node S1 is at a high level, that is, the drain of the P-channel MOSFET 11 and the N-channel MOSFET
The voltage is substantially equal to the voltage at the common connection point of the drains 12 and 13 (region A).

On the other hand, when the power supply voltage VDD is higher than the predetermined voltage and the output voltage of the node S2 of the voltage dividing circuit 2 is higher than the output voltage of the node S3 of the reference voltage generating circuit 3, the gate voltage of the N-channel MOSFET 16 is In comparison, the gate voltage of the N-channel MOSFET 15 becomes excessive. Therefore, the output voltage of the node S1 is low level, that is,
The voltage becomes substantially equal to the drain voltage of the N-channel MOSFET 14 (region B). FIG. 2 shows that VDD = 3.5 V
A state where the voltage of the node S1 changes from a high level to a low level in the vicinity is shown.

As described above, in the power supply voltage detection circuit described above, a high-level signal is output from the node S1 when the power supply voltage of the IC is lower than a predetermined value, and a low-level signal is output when the power supply voltage is higher than the predetermined value. Is done.

Thus, in a semiconductor integrated circuit having a plurality of circuits having different drive timings, first, the number of stages of the timing compensation delay circuit for optimizing the drive order of each circuit can be switched. Keep it. Then, the node S1 of the above-described power supply voltage detection circuit
When a low-level signal is output from the power supply (when the power supply voltage is higher than a predetermined value), the operation speed is improved by reducing the number of stages of the delay circuit to the minimum necessary number.
Further, when a high-level signal is output from the node S1 (when the power supply voltage is lower than a predetermined value), the number of stages of the delay circuit is increased to reliably prevent a malfunction in timing.

As described above, according to the semiconductor integrated circuit of the present embodiment, the timing for making the drive order of each circuit in the semiconductor integrated circuit appropriate in accordance with the change in the supplied power supply voltage. Since the switching can be performed as appropriate, the semiconductor integrated circuit can exhibit its intended function regardless of the power supply voltage.

[0023]

As described above, according to the present invention, the power supply voltage to be supplied is detected, and based on the detection result, the driving order of each circuit in the semiconductor integrated circuit is made appropriate. Since the timing is appropriately switched, it is possible to control the semiconductor integrated circuit to exhibit a desired function irrespective of the power supply voltage. Therefore, in realizing a semiconductor integrated circuit that operates with a wide range of power supply voltages, it is not necessary to manufacture semiconductor integrated circuits corresponding to each power supply voltage, and to manufacture a semiconductor integrated circuit with a wide power supply voltage range at low cost. Is obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a power supply voltage detection circuit provided in a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a simulation result of the operation of the power supply voltage detection circuit.

[Explanation of symbols]

1... Comparison circuit, 2... Voltage divider circuit, 3, 4... Reference voltage generation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03K 5/14 H01L 27/04 B 19/00

Claims (1)

[Claims] 1. A semiconductor integrated circuit including a plurality of circuits having different drive timings, a voltage divider for dividing a power supply voltage and outputting the divided voltage, a reference voltage generator for outputting a reference voltage, and an output of the voltage divider. Comparing the voltage with the reference voltage,
A comparison circuit that outputs the comparison result as a control signal; and a timing compensation circuit that includes a plurality of delay circuits, switches the number of the delay circuits according to the control signal, and compensates the drive timing of the plurality of circuits. A semiconductor integrated circuit characterized by the above.