JP2010028244A - Hysteresis comparator circuit and delay circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain long delay time without enlarging a circuit scale. <P>SOLUTION: The input signals Vin of the rectangular waves of a delay object are converted to trapezoidal wave signals Vc by a trapezoidal wave generation circuit 10, and the trapezoidal wave signals Vc and first and second threshold voltages are compared in an inverter 21 having a first threshold voltage Th1 set higher than the intermediate voltage of the trapezoidal wave signals and an inverter 22 having a second threshold voltage Th2 set lower than the intermediate voltage. A buffer circuit 23 is driven by the output of the inverter 21 and the inverter 22, and the output signals Vout of the rectangular waves inverted and delayed in synchronism with the trapezoidal wave signals Vc are generated. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a hysteresis comparator circuit and a delay circuit using the same, and more particularly to a technique suitable for increasing the delay time of a rectangular wave signal without increasing the circuit scale.

  Conventionally, a delay circuit for delaying a rectangular wave signal has been used for various purposes. As such a delay circuit, for example, as described in Patent Document 1, an inverter that charges and discharges a capacitor at the rising and falling timing of a rectangular wave signal to be delayed and is turned on / off by the terminal voltage of the capacitor A circuit is provided. According to this, the charge / discharge current of the capacitor is variably controlled to control the slope of the rise or fall of the capacitor voltage, thereby generating a trapezoidal wave signal synchronized with the input rectangular wave signal. A trapezoidal wave signal can be shaped by an inverter circuit that uses the intermediate voltage of the signal as a threshold voltage Vth to generate a rectangular wave signal with a variable delay time.

JP 2007-6254 A

  By the way, according to the method of the prior art such as Patent Document 1, the delay time of the rectangular wave signal is when charging / discharging so that the terminal voltage of the capacitor changes in a triangular wave shape, and the period of the rectangular wave signal is 1/4 is the maximum delay time.

  Therefore, when it is desired to delay more than ¼ of the period of the rectangular wave signal, the delay circuit is delayed by a multistage delay circuit in which a plurality of similar delay circuits are connected in series. In particular, when the rectangular wave signal is a high-frequency signal, the signal cycle is short, and thus the maximum delay time per stage is short. Therefore, in order to obtain a required delay time, it is necessary to use multiple delay circuits. In that case, since the circuit scale of the delay circuit is increased, the number of elements constituting the circuit is increased, and there is a problem that the delay time varies due to variations in characteristics of these elements.

  The problem to be solved by the present invention is to obtain a large delay time without increasing the circuit scale.

  In order to solve the above problems, the present invention is characterized in that a hysteresis comparator circuit suitable for a delay circuit is configured. That is, the hysteresis comparator circuit of the present invention has a first threshold voltage set higher than the intermediate voltage of the input trapezoidal wave signal and a second threshold voltage set lower than the intermediate voltage, The trapezoidal wave signal is compared with the first and second threshold voltages, and a rectangular wave output signal that is inverted and delayed in synchronization with the trapezoidal wave signal is generated.

  That is, the hysteresis comparator circuit of the present invention includes a first threshold voltage set higher than the intermediate voltage of the trapezoidal wave signal such as a capacitor terminal voltage, and a second threshold set lower than the intermediate voltage of the trapezoidal wave signal. Comparing the voltage and the trapezoidal wave signal, for example, outputting the output signal that rises when the trapezoidal wave signal exceeds the first threshold voltage and falls when the trapezoidal wave signal falls below the second threshold voltage. . For example, the delay time T of the output signal Vout with respect to the input signal Vin to be delayed is determined by the time from the rising edge of the trapezoidal wave signal Vc output from the trapezoidal wave generating circuit to the threshold voltage Th1 of the hysteresis comparator circuit.

  Therefore, by using a hysteresis comparator circuit in which the threshold voltage Th1 is higher than the intermediate voltage Vc at the time of rising with respect to the trapezoidal wave signal Vc and the threshold voltage Th2 is lower than the intermediate voltage of Vc at the time of falling, both rising and falling are used. Compared with the prior art using the same intermediate voltage threshold voltage, the delay time can be increased.

  In this case, the hysteresis comparator circuit is connected in series between the power source and the ground, and the first CMOS inverter and the second CMOS inverter are connected between the power source and the ground, respectively, and the trapezoidal wave signal is input to the gate, respectively. An output circuit that outputs a rectangular wave signal that is synchronized with the trapezoidal wave signal and delayed by a set time from a common connection point of PMOS and NMOS, and that includes the first CMOS inverter and the second CMOS inverter. The threshold voltages are set to the first threshold voltage and the second threshold voltage, respectively, the output of the first CMOS inverter is input to the PMOS gate of the output circuit, and the NMOS gate of the output circuit is input. The output of the second CMOS inverter can be input. That.

  Further, in this case, the first threshold voltage and the second threshold voltage are variably set by varying the current driving capabilities of the PMOS and NMOS constituting the first CMOS inverter and the second CMOS inverter. It can be configured.

  Further, the first threshold voltage and the second threshold voltage can be varied. In this case, for example, a plurality of inverters having different threshold voltages corresponding to the first threshold voltage and the second threshold voltage are provided, and the inverters are selected to vary the first threshold voltage and the second threshold voltage. It can be configured.

  The delay circuit of the present invention includes any one of the hysteresis comparator circuits described above, and charges and discharges the capacitor in synchronization with the input signal of the rectangular wave to be delayed as a trapezoidal wave signal that is an input signal thereof. And a trapezoidal wave generating circuit that outputs a capacitor terminal voltage obtained by controlling the charge / discharge current of the capacitor.

  According to the present invention, a large delay time can be obtained without increasing the circuit scale.

  The delay circuit of the present invention will be described below based on examples.

  FIG. 1 shows a block diagram of a delay circuit according to one embodiment of the present invention, and FIG. 2 shows a circuit diagram of a specific example of this embodiment.

  As shown in FIG. 1, the delay circuit of the present embodiment is a trapezoid having a rising angle and a falling angle based on a signal Ictrl that is synchronized with an input signal Vin of a rectangular wave and that controls the delay time. A trapezoidal wave generation circuit 1 that generates a signal Vc of a wave voltage, and a hysteresis comparator circuit 2 that outputs an output signal Vout obtained by delaying the input signal Vin for a set time based on the signal Vc output from the trapezoidal wave generation circuit 1 Configured.

  As the trapezoidal wave generation circuit 1, a known trapezoidal wave generation circuit 10 shown in FIG. 2 can be used. That is, as shown in FIG. 2, the trapezoidal wave generating circuit 10 includes a series circuit of a PMOS element M1, a constant current source 11, and an NMOS element M2 connected between the control power supply VDD and the ground. The constant current source 11 supplies a current corresponding to the signal Ictrl for controlling the delay time. The trapezoidal wave generation circuit 10 includes PMOS elements M3 and M4 and NMOS elements M5 and M6 connected in series between the control power supply VDD and the ground. The gates of M1 and M3 are commonly connected to the positive side of the constant current source 11, and the gates of M2 and M6 are commonly connected to the negative side of the constant current source 11, so that M1 and M3, and M2 and M6 each have a current mirror. It is composed. Further, the input signal Vin to be delayed is input to the gates of M4 and M5, and the series connection point of M4 and M5 is grounded via the capacitor C.

  Thereby, M4 and M5 are turned on and off in synchronization with the rectangular wave input signal Vin shown in FIG. When M4 is on, the capacitor C is charged with a constant current corresponding to the signal Ictrl. When M4 is on, the capacitor C is discharged with a constant current corresponding to the signal Ictrl. As a result, a trapezoidal wave voltage Vc that is a terminal voltage of the capacitor C synchronized with the input signal Vin is input to the hysteresis comparator circuit 20 as shown in FIG.

  The hysteresis comparator circuit 20 includes a first CMOS inverter 21 and a second CMOS inverter 22 that are connected between the control power supply VDD and the ground, respectively, and in which the trapezoidal wave voltage Vc is commonly input to the gates, and an output circuit 23. It is configured. The first CMOS inverter 21 includes a PMOS element M9 and an NMOS element M10, and the second CMOS inverter 22 includes a PMOS element M7 and an NMOS element M8.

  Here, the current drive capability of M9 is set larger than the current drive capability of M10, and as a result, the threshold voltage Th1 of the first CMOS inverter 21 is set higher than the intermediate voltage of the trapezoidal wave voltage Vc. . Further, the current drive capability of M8 is set to be larger than that of M7, and as a result, the threshold voltage Th2 of the second CMOS inverter 22 is set lower than the intermediate voltage of the trapezoidal wave voltage Vc.

  On the other hand, the output circuit 23 includes a PMOS element M11 and an NMOS element M12 connected in series between the control power supply VDD and the ground. The output of the first CMOS inverter 21 is inputted to the gate of M11, and the gate of M12 is inputted. The output of the second CMOS inverter 22 is input. Thereby, M11 is turned on / off by the output of the first CMOS inverter 21, and M12 is turned on / off by the output of the second CMOS inverter 22. Further, a series connection point of M11 and M12 is connected to the output terminal 24, and a delayed output signal Vout is output.

  The operation of the first embodiment configured as described above will be described with reference to the waveform diagram of FIG. As described above, when M4 and M5 are turned on and off in synchronization with the rectangular wave input signal Vin shown in FIG. 3A, the capacitor C is charged and discharged with a constant current corresponding to the signal Ictrl. As a result, as shown in FIG. 3B, the capacitor C is discharged in synchronization with the rising edge of the input signal Vin, and the capacitor C is charged in synchronization with the falling edge of the input signal Vin. As a result, the trapezoidal wave voltage Vc that is the terminal voltage of the capacitor C is input to the hysteresis comparator circuit 20.

  In the hysteresis comparator circuit 20, as shown in FIG. 3C, when the trapezoidal wave voltage Vc falls below the threshold voltage Th1 of the first CMOS inverter 21, the output of the first CMOS inverter 21 becomes "H" and M11 Is turned off and exceeds the threshold voltage Th1, the output of the first CMOS inverter 21 becomes "L" and M11 is turned on. On the other hand, as shown in FIG. 3 (d), when the trapezoidal wave voltage Vc falls below the threshold voltage Th2 of the second CMOS inverter 22, the output of the second CMOS inverter 22 becomes "H" and M12 is turned on. When the threshold voltage Th2 is exceeded, the output of the second CMOS inverter 22 becomes "L" and M12 is turned off.

  Here, when M11 is on, the output signal Vout is at "H" level, when M12 is on, the output signal Vout is at "L" level, and when both M11 and M12 are off, the previous state depends on the parasitic capacitance or load capacitance. Is retained. As a result, the output signal Vout becomes as shown in FIG. 3E, and the input signal Vin becomes the output signal Vout delayed by the delay time T.

  That is, the delay time T of the output signal Vout with respect to the input signal Vin is determined by the time from the rise of the trapezoidal wave voltage Vc output from the trapezoidal wave generation circuit 10 to the threshold voltage Th1 of the first CMOS inverter 21 in the next stage. . In other words, by using a hysteresis comparator circuit in which the threshold voltage Th1 is higher than the intermediate voltage of Vc at the rising time with respect to the trapezoidal wave voltage Vc and the threshold voltage Th2 is lower than the intermediate voltage of Vc at the falling time, both rising and falling are used. Compared with the prior art using the same intermediate voltage threshold voltage, a large delay time can be obtained without increasing the circuit scale.

  It goes without saying that the delay circuit of this embodiment can be formed together with other circuits on a single semiconductor substrate such as single crystal silicon by a semiconductor integrated circuit manufacturing technique.

  FIG. 4 shows a block diagram of a delay circuit according to another embodiment of the present invention, and FIG. 5 shows a block diagram of a hysteresis comparator circuit according to this embodiment.

  As shown in FIG. 4, this embodiment is different from the first embodiment of FIG. 1 in that the threshold voltages Th1 and Th2 of the hysteresis comparator circuit 3 can be variably set by the control signal Vtin of the threshold voltage. is there.

  The hysteresis comparator circuit 3 of the present embodiment includes an inverter circuit 31 and an inverter circuit 32 as shown in the block diagram of FIG. The inverter circuit 31 is configured to vary the threshold voltage based on the input control signal Vtin. That is, the threshold voltage Th1 for detecting the rise of Vc output from the trapezoidal wave generation circuit 1 and the threshold voltage Th2 for detecting the fall are varied, and the output signal 33 output from the inverter circuit 31 has hysteresis characteristics. Can be made. The inverter circuit 32 inverts the output signal 33 and outputs an output signal Vout delayed for a time corresponding to the threshold voltages Th1 and Th1 with respect to the input signal Vin.

  According to the present embodiment, as in the first embodiment, the threshold voltage Th1 is higher than the intermediate voltage Vc at the time of rising with respect to the trapezoidal wave voltage Vc, and the threshold voltage Th2 is lower than the intermediate voltage of Vc at the falling time. By using the comparator circuit, it is possible to obtain a large delay time without increasing the circuit scale as compared with the conventional technique using the same threshold voltage for both rising and falling.

  FIG. 6 shows a circuit configuration diagram of a specific embodiment applicable to the hysteresis comparator circuit 3 of the embodiment 2 of FIG. As shown in the figure, the hysteresis comparator circuit 30 includes an inverter circuit 35 and an inverter circuit 36. The inverter circuit 35 connects a series circuit of PMOS elements M21 and M22 and NMOS elements M23 and M24 between the control power supply VDD and the ground, and outputs them from the trapezoidal wave generating circuit 1 to the gates of M21 to M24. Vc to be input is input. A PMOS element M25 is connected in parallel to M21, and an NMOS element M26 is connected in parallel to M24. The potential at the common connection point of M22 and M23 is the output signal 37 of the inverter circuit 35.

  On the other hand, the inverter circuit 36 connects a series circuit of a PMOS element M27 and an NMOS element M28 between the control power supply VDD and the ground, and the output signal 37 of the inverter circuit 35 is input to the gates of these M27 and 28. ing. The potential at the common connection point of M27 and M28 is the output signal Vout of the inverter circuit 36. Further, the output signal Vout is fed back to the gates of M25 and M26 of the inverter circuit 35 as the control signal Vtin. Thereby, the inverter circuit 35 is configured to vary the threshold voltages Th1 and Th2.

  The operation of this embodiment configured as described above will be described. Since M25 is turned on when Vout is “L”, the drain and source of M21 are short-circuited. Thus, the threshold voltage of the inverter circuit 35 is determined by the inverse ratio of the current drive capability ratio of M22 and (M23 + M24). Therefore, the length L and width W of the MOS channels are set so that the threshold voltage Th1 is higher than the intermediate voltage Vc. On the contrary, when Vout is “H”, M26 is turned on and the drain-source of M24 is short-circuited, so the threshold voltage is determined by the inverse ratio of the current drive capability ratio of (M21 + M22) and M23. Therefore, the length L and width W of the MOS channels are set so that the threshold voltage Th2 is lower than the intermediate voltage Vc.

  Here, if the input voltage Vc of the inverter circuit 35 is “H”, the output signal 37 of the inverter circuit 35 becomes “L”, and the output signal Vout of the inverter 36 becomes “H”. Thereby, the threshold voltage Th2 at the time of falling of the input voltage Vc is set low. Next, when the input voltage Vc becomes “L”, the output signal 37 of the inverter circuit 35 becomes “H”, the output signal Vout of the inverter 36 becomes “L”, and the threshold voltage Th1 at the rise of the input voltage Vc is high. Is set.

  In this way, according to the hysteresis comparator circuit 30 of the present embodiment, the threshold voltages Th1 and Th2 change depending on the rising and falling of the input voltage Vc, so that hysteresis characteristics are exhibited.

  In FIG. 7, an example of the operation | movement waveform of a present Example is shown. As shown in the figure, when the input voltage Vc is input from the trapezoidal wave generating circuit 1, an output signal 37 is output from the inverter circuit 35, and thereby an output signal Vout is output from the inverter circuit 36.

  According to the hysteresis comparator circuit 30 of the present embodiment, since the hysteresis comparator circuit can be configured without using the operational amplifier, the bias current necessary for the operational amplifier is not required. A circuit can be realized.

  FIG. 8 shows a circuit configuration diagram of still another embodiment applicable to the hysteresis comparator circuit 3 of the second embodiment shown in FIG. As shown in the figure, the hysteresis comparator circuit 40 of this embodiment includes a plurality of N (N is a natural number of 2 or more) inverter circuits Inv1 to InvN to which the input voltage Vc is input from the trapezoidal wave generation circuit 1, and inverters A selector circuit 41 that switches and outputs the outputs of the circuits Inv1 to InvN according to the control signal Vctrl, a PMOS element M41 that is turned on / off by the output signals 42 and 43 of the selector circuit 41, and a buffer circuit formed by connecting the PMOS element M42 in series 44 is formed. Then, the inverter circuits Inv1 to InvN are switched and selected by the control signal Vctrl, and an inverter circuit having desired threshold voltages Th1 and Th2 is selected.

  Therefore, according to the present embodiment, since the threshold voltages Th1 and Th2 can be changed and set by the control signal Vctrl, the delay time can be easily variably set by applying to the delay circuit.

  The hysteresis comparator circuit of the present invention has been described based on the embodiment applied to the rectangular wave signal delay circuit, but it goes without saying that the hysteresis comparator circuit can be used alone.

The block diagram of the delay circuit of one Example of this invention is shown. The circuit block diagram of a specific example of the Example of FIG. 1 is shown. FIG. 3 is a waveform diagram of each part for explaining the operation of the embodiment of FIG. 2. The block block diagram of the delay circuit of the other Example of this invention is shown. FIG. 5 is a block diagram illustrating an example of a hysteresis comparator circuit according to the embodiment of FIG. 4. The circuit block diagram of the concrete Example applicable to the hysteresis comparator circuit of the Example of FIG. 4 is shown. FIG. 7 is a waveform diagram of each part for explaining the operation of the hysteresis comparator circuit of FIG. 6. The circuit block diagram of the further another Example applicable to the hysteresis comparator circuit of the Example of FIG. 4 is shown.

Explanation of symbols

1, 10 Trapezoidal wave generator 2, 3, 20 Hysteresis comparator circuit

Claims (8)

  A first threshold voltage set higher than an intermediate voltage of the input trapezoidal wave signal, and a second threshold voltage set lower than the intermediate voltage, and the trapezoidal wave signal and the first and second threshold voltages A hysteresis comparator circuit that compares the threshold voltages of the two and generates a rectangular wave output signal that is inverted in synchronization with the trapezoidal wave signal and delayed. The hysteresis comparator circuit according to claim 1,
The hysteresis comparator circuit, wherein the output signal is a signal that rises when the trapezoidal wave signal exceeds a first threshold voltage and falls when the trapezoidal wave signal falls below a second threshold voltage. . The hysteresis comparator circuit according to claim 1,
The hysteresis comparator circuit includes a first CMOS inverter and a second CMOS inverter that are respectively connected between a power source and a ground and the trapezoidal wave signal is input to a gate, and a PMOS and an NMOS connected in series between the power source and the ground An output circuit that outputs a rectangular wave signal that is synchronized with the trapezoidal wave signal from the common connection point and is delayed for a set time,
The threshold voltages of the first CMOS inverter and the second CMOS inverter are set to the first threshold voltage and the second threshold voltage, respectively, and the first CMOS inverter is connected to the PMOS gate of the output circuit. Is output, and the output of the second CMOS inverter is input to the NMOS gate of the output circuit. The hysteresis comparator circuit according to claim 3,
The first threshold voltage and the second threshold voltage are variably set with different current driving capabilities of PMOS and NMOS constituting the first CMOS inverter and the second CMOS inverter. Comparator circuit. The hysteresis comparator circuit according to claim 1,
The hysteresis comparator circuit, wherein the first threshold voltage and the second threshold voltage are variable. The hysteresis comparator circuit according to claim 5,
A plurality of inverters having different threshold voltages corresponding to the first threshold voltage and the second threshold voltage; and selecting the inverters to vary the first threshold voltage and the second threshold voltage. A hysteresis comparator circuit. The hysteresis comparator circuit according to claim 1,
The hysteresis comparator circuit includes first and second PMOSs, third and fourth NMOSs connected in series between a power source and the ground, a fifth PMOS connected in parallel to the first PMOS, and the fourth PMOSs. A first inverter composed of a sixth NMOS connected in parallel to the NMOS; and a second inverter composed of PMOS and NMOS connected in series between the power source and the ground. The trapezoidal wave signal is input to the gates of the PMOS and the third and fourth NMOSs, the voltage at the common connection point of the PMOS and NMOS of the second inverter is used as the output signal, and the output signal is used as the first inverter. A rectangular wave output signal that is input to the gates of the fifth PMOS and the sixth NMOS and is synchronized with the trapezoidal wave signal and delayed by a set time. Steri-cis comparator circuit. A hysteresis comparator circuit according to any one of claims 1 to 7,
The trapezoidal wave signal includes a trapezoidal wave generating circuit that charges and discharges a capacitor in synchronization with the input signal of the rectangular wave to be delayed and outputs a capacitor terminal voltage obtained by controlling the charge / discharge current of the capacitor. Delay circuit.

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