JPH07154231A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a radiation noise and a crosstalk noise by connecting plural diodes for voltage drop in series to a power supply line of a P-channel MOS transistor(TR) in a positive polarity. CONSTITUTION:P-channel and N-channel MOS TRs 2, 3 are connected in parallel with an internal logic 1 inserted between a power supply terminal 6 and a ground terminal 7 and gate electrodes of the TRs 2,3 are connected to an output of the internal logic 1. Furthermore, a power supply line of the P-channel MOS TR 2 is connected to a voltage drop diode 5 in a positive polarity and the voltage drop diode 5 consists of plural diodes 5a connected in series in positive polarity. When an output of the circuit is at a high level, the P-channel MOS TR 2 is conductive and a voltage is applied to an output terminal 4 from the power supply terminal 6, then a predetermined voltage drop per each diode is produced because of the forward voltage drop of the voltage drop diode 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to an output circuit of a CMOS IC that operates at high speed.

[0002]

2. Description of the Related Art Conventionally, the output circuit of this type of CMOS IC is composed of a P-channel MOS transistor 2 and an N-channel MOS transistor 3 as shown in FIG. 2 is turned on, the N-channel MOS transistor 3 is turned off, and a voltage close to the power supply voltage is output to the output terminal 4.

[0003]

This conventional CMOS
In the output circuit of the IC, since the amplitude level of the output signal is large, a high frequency component in a high speed circuit such as a clock line is large and causes radiation noise and crosstalk noise.

Originally, in the TTL level interface circuit, the signal amplitude does not need to be 3 V or more.
If the threshold voltage of TTL is 1.4V, if the high level is 2V or more and the low level is 0.8V or less, the operation is sufficient.

Therefore, it is desirable to suppress the output level of the CMOS IC to 3 V or less at a high level from the viewpoint of reducing radiation noise and crosstalk noise. In particular, the amplitude of a line such as a clock line, which is a problem as a noise source, needs to be as small as possible.

As disclosed in Japanese Patent Laid-Open No. 62-287660, a technique has already been proposed for lowering the input threshold level by connecting a voltage drop element in series to the power source line of a transistor forming an input circuit. However, an example in which a voltage drop element is used in the output circuit to suppress the amplitude of the output waveform to a low level has not been proposed yet.

Therefore, the present invention solves such a problem and provides a semiconductor integrated circuit which lowers the high level output voltage of the output circuit of a CMOS IC and suppresses the generation of radiation noise and crosstalk noise. The purpose is to do.

[0008]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention has an internal logic inserted between a power supply terminal and a ground terminal in an output circuit of the semiconductor integrated circuit. A P-channel MOS transistor and an N-channel MOS transistor are connected in parallel with the P-channel M transistor on the output side of the internal logic.
Gate electrodes of both the OS transistor and the N-channel MOS transistor are connected, and a plurality of step-down diodes are connected in a forward direction and in series to the power supply line of the P-channel MOS transistor.

[0009]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a semiconductor integrated circuit which is an embodiment of the present invention.

In this semiconductor integrated circuit, in FIG. 1, an internal logic 1 is inserted between a power supply terminal 6 and a ground terminal 7, and a P channel M is arranged in parallel with the internal logic 1.
The OS transistor 2 and the N-channel MOS transistor 3 are connected, and the gate electrodes of both the P-channel MOS transistor 2 and the N-channel MOS transistor 3 are connected to the output side of the internal logic 1. Also P
A step-down diode 5 is connected to the power supply line of the channel MOS transistor 2 in the forward direction. This step-down diode 5 has a plurality of diodes 5a connected in series in the forward direction. In this embodiment, four diodes 5a are connected in series. Here, the circuit configuration of the present invention will be specifically described.

In this circuit, the power supply terminal 6 is connected to one end of the internal logic 1, and further connected to the cathode terminal of the step-down diode 5. Also, P channel MOS
The source electrode of the transistor 2 is connected to the step-down diode 5 described above.
Connect to the anode terminal of and connect the gate electrode to the internal logic 1
Is connected to the output side of.

The ground terminal 7 is connected to the ground side terminal of the internal logic 1 and also to the source electrode of the N-channel MOS transistor 3, and the gate electrode of the N-channel MOS transistor 3 is connected to the output side of the internal logic 1. Are connected.

The output terminal 4 is connected to both the drain electrode of the P-channel MOS transistor 2 and the drain electrode of the N-channel MOS transistor 3.

Next, the operation of the semiconductor integrated circuit of the present invention having the above configuration will be described.

The output signal output from the internal logic 1 is switched by the P-channel MOS transistor 2 and the N-channel MOS transistor 3 to output the output terminal 4.
Is output to.

When the output of the circuit of the present invention is at a high level, P
The channel MOS transistor 2 is turned on and a voltage is applied to the output terminal 4 from the power supply terminal 6,
At this time, the forward voltage drop of the step-down diode 5 causes a voltage drop of about 0.6 V per diode. When the step-down diode 5 has four stages, the total voltage drop is 0.6 × 4 = 2.4V, and the voltage output to the output terminal 4 is the power supply voltage −2.4V.

In many cases, 5V is usually used as the power supply voltage, and in that case, the high level output voltage is 5V-2.4V =
It becomes 2.6V. This is about half the output level of the conventional CMOS IC when the output level is about 5V, and the high frequency noise in question is 2.6 / 5 times as large, that is, -5.6d.
B is decreased.

Next, a second embodiment of the present invention will be described with reference to FIGS. 2 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention, FIG. 3 is a diagram showing a usage example of the second embodiment, and FIG. 4 is an output waveform diagram when the circuit of FIG. 3 is used. FIG. 5 is a diagram showing another example of use of the second embodiment, and FIG. 6 is an output waveform diagram when the circuit of FIG. 5 is used.

In the second embodiment shown in FIG. 2, an output voltage switching transistor 8 for varying the voltage value output to the output terminal 4 is connected in parallel to both ends of each element of the step-down diode 5, and further the internal Also connected to Logic 1. That is, the source electrode of the output voltage switching transistor 8 is connected to the cathode terminal of the diode 5a, the drain electrode is connected to the anode terminal, and the gate electrode is connected to the internal logic 1. The output voltage switching transistor 8 is connected between the diodes 5a. In the case of the second embodiment, the output voltage switching transistor 8 is composed of a first transistor 8a, a second transistor 8b and a third transistor 8c. However, the third transistor 8c is connected between the two diodes on the source electrode side of the P-channel MOS transistor 2.

In the circuit thus constructed, the output voltage switching transistor 8 is turned on or off by the control signal from the internal logic 1, the step-down diode 5 is bypassed as necessary, and the output terminal 4 is connected to the output terminal 4. Switch the output voltage. In the circuit shown in FIG. 2, the output voltage can be switched in four steps.

Here, an example using the second embodiment will be described with reference to FIG. The output is connected to the input side IC 10 through the high speed clock line 9. In this case, the high-speed clock line 9 contains a lot of high-frequency components and becomes a noise source. Therefore, it is necessary to make the output amplitude as small as possible. Therefore, the first transistor 8a, the second transistor 8b, and the third transistor 8c are turned off.
The F state is set, all the step-down diodes 5 are made effective, and an output waveform as shown in FIG. 4 is obtained.

FIG. 5 shows another example of use of the second invention. Output terminal 4 receives active low signal IC1 on receiving side
In the case of transmission to 2, the high level should be set high in order to prevent malfunction when noise 11 enters the transmission line in the middle. In such a case, by turning on the first transistor 8a, turning on the second transistor 8b, and turning off the third transistor 8c in FIG. 3, only two of the four step-down diodes can be enabled.
The high level voltage output to the output terminal 4 is the power supply voltage −
It becomes (0.6 × 2) V, and becomes 3.8V when the power supply voltage is 5V.

Here, the output waveform in the use example of FIG. 5 is shown in FIG. The high-side margin is larger than the threshold level, making it less susceptible to noise.

[0024]

As described above, according to the present invention, since the amplitude of the output waveform can be suppressed to a low level, the level of the higher harmonics of the signal can be lowered and the radiation noise and crosstalk noise can be reduced. Further, since the output level can be arbitrarily selected, it is possible to obtain the optimum output amplitude in consideration of the noise margin against external noise and the level of radiated noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit that is an embodiment of the present invention.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit that is a second embodiment of the present invention.

FIG. 3 is a diagram showing an example of use of a second embodiment.

FIG. 4 is an output waveform diagram when the circuit of FIG. 3 is used.

FIG. 5 is a diagram showing another usage example of the second embodiment.

FIG. 6 is an output waveform diagram when the circuit of FIG. 5 is used.

FIG. 7 is an output circuit diagram of a conventional CMOS IC.

[Explanation of symbols]

 1 Internal logic 2 P-channel MOS transistor 3 N-channel MOS transistor 5 Step-down diode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H03K 19/0185 19/0948 8839-5J H03K 19/094 B

Claims (2)

[Claims] 1. In an output circuit of a semiconductor integrated circuit, an internal logic is inserted between a power supply terminal and a ground terminal, and a P-channel MOS transistor and an N-channel MOS transistor are connected in parallel with the internal logic.
Gate electrodes of both the P-channel MOS transistor and the N-channel MOS transistor are connected to the output side of the internal logic, and a plurality of step-down diodes are connected in a forward direction and in series to a power supply line of the P-channel MOS transistor. A semiconductor integrated circuit characterized by being connected to. 2. A switching element for switching an output voltage is connected in parallel to both ends of each element of the plurality of step-down diodes, and a gate electrode of the switching element is connected to the internal logic. The semiconductor integrated circuit according to claim 1.