JPH02122724A - Level conversion circuit - Google Patents
Level conversion circuitInfo
- Publication number
- JPH02122724A JPH02122724A JP63276422A JP27642288A JPH02122724A JP H02122724 A JPH02122724 A JP H02122724A JP 63276422 A JP63276422 A JP 63276422A JP 27642288 A JP27642288 A JP 27642288A JP H02122724 A JPH02122724 A JP H02122724A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- diode
- voltage
- electrode
- vdd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
Abstract
PURPOSE:To prevent current consumption in a fast operation from being increased by providing a PMOS transistor whose gate electrode is connected to an input terminal, whose source electrode to the cathode side terminal of a diode, and whose drain electrode to an output terminal. CONSTITUTION:The gate electrode of the PMOS transistor 4 is connected to the input terminal 1, and the source electrode to the cathode side terminal of the diode 3, and the drain electrode to the output terminal 5. Meanwhile, the gate electrode of an NMOS transistor 6 is connected to the terminal 1, and the source electrode to the anode side terminal of the diode 7, and the drain electrode to the terminal 5. In such a constitution, assuming the potential of a negative power source 8 as 0 and that of a positive power source as VDD, the voltage of the terminal 5 goes to a value less than the VDD by the voltage drop of the diode 3 when the voltage of the terminal 1 is VDD. Also, when the voltage of the terminal 1 is 0, the voltage of the terminal 1 goes to the value larger than 0 by the voltage drop of the diode 3, which reduces the amplitude of the terminal 5, Therefore, it is possible to prevent the current consumption from being increased even in the fast operation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63276422A JPH02122724A (en) | 1988-10-31 | 1988-10-31 | Level conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63276422A JPH02122724A (en) | 1988-10-31 | 1988-10-31 | Level conversion circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02122724A true JPH02122724A (en) | 1990-05-10 |
Family
ID=17569192
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63276422A Pending JPH02122724A (en) | 1988-10-31 | 1988-10-31 | Level conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02122724A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07154231A (en) * | 1993-11-25 | 1995-06-16 | Nec Corp | Semiconductor integrated circuit |
US5942915A (en) * | 1996-09-09 | 1999-08-24 | Nec Corporation | Level shift circuit formed by two cascaded CMOS inverters |
-
1988
- 1988-10-31 JP JP63276422A patent/JPH02122724A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07154231A (en) * | 1993-11-25 | 1995-06-16 | Nec Corp | Semiconductor integrated circuit |
US5942915A (en) * | 1996-09-09 | 1999-08-24 | Nec Corporation | Level shift circuit formed by two cascaded CMOS inverters |
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