JPS639222A - Transfer gate circuit - Google Patents

Abstract

PURPOSE:To improve the reliability of a transfer gate circuit by specifying the current direction of a current path by two MOS transistors (TRs) via a control gate. CONSTITUTION:Each of n-channel MOS TRs 11, 12 forming a transfer gate is controlled respectively by a NOR gate 13 receiving a clock phi and a data and a NOR gate 14 receiving an output of the gate 13 and th data. Thus, the current direction flowing to the TRs 11, 12 is specified, the source and drain of the TRs 11, 12 always act like the source and drain, thereby forming the transfer gate circuit with high reliability not largely receiving the effect of characteristic discrimination by a hot carrier effect.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a transfer gate circuit configured using MOS transistors.

(Prior art) □ In recent years, the scale of semiconductor integrated circuits and the miniaturization of elements have been remarkable. MO8 integrated circuits have many problems due to the miniaturization of elements, and among them, M due to hot carriers.
Deterioration of characteristics of o8 T-transistors has become a major problem. In particular, the transformer 77 gate circuit is extremely sensitive to characteristic deterioration due to hot carriers. The reason is as follows.

Impact ionization of a MOS transistor occurs on the drain region side where a high electric field is formed, and hot carriers generated thereby are injected into the gate insulating film from the train region. In the case of an n-channel MOS transistor, electrons are injected into the gate insulating film on the drain region side and are trapped. As a result, M
This causes a decrease in the threshold value and mutual conductance of the OS transistor. However, the transfer gate circuit
The Mo8 t-transistor is used bidirectionally.

That is, assuming that the source and drain regions are fixed, in the transfer gate, current flows from the drain region to the source region at a certain timing, and from the source region to the drain region at another timing.

The static characteristics of the Mo8 t-transistor before deterioration are shown as A in Figure 5, and the characteristics in the mode where the original drain operates as a drain after hot carriers are injected into the gate insulating film on the drain region side are shown as B. If so, on the other hand, in the mode where the source operates as a drain, the characteristic is C
become that way. This is because in the pentode operating region of the Mo8t-transistor, the depletion layer extends from the drain region, so the characteristics of the gate insulating film on the channel region near the train region do not significantly affect the static characteristics, whereas This is because the characteristics of the side channel region determine the static characteristics of the Mo3 transistor, so if a deteriorated MOS transistor is used with the source and drain regions reversed, a large influence will appear.

(Problems to be Solved by the Invention) As described above, the conventional transfer gate circuit that bidirectionally uses the Mo8 t-transistor has a problem in that it is extremely affected by characteristic deterioration due to hot carriers.

An object of the present invention is to provide a transfer gate circuit that solves these problems.

[Structure of the Invention] (Means for Solving the Problems) A transfer gate circuit according to the present invention has two MOS transistors connected together that are controlled by a clock signal, and at least one of these Mo8 t-transistors It is characterized by having a subsurface gate that specifies the current direction.

(Function) With the above configuration, the MO with the specified current direction
In an S transistor, the drain is always used as a train and the source is always used as a source. Therefore, it is possible to obtain an excellent transfer game circuit which is not significantly affected by characteristic deterioration due to the hot carrier effect.

(Example) The present invention will be explained in detail below.

FIG. 1 is an equivalent circuit of a transfer gate circuit of one embodiment. The first terminal Nl, which is a data input/output terminal, and the second terminal
Two n-channel MOS transistors 11 and 12 are provided between terminals N2 of . Noah Gate 13.14
constitutes a control gate that controls the MOS transistors 11 and 12 in order to specify the flow direction thereof.

The first terminal N1 is a high level, and the second terminal N2 is a low level.
When the clock signal φ is at L II level, the output of NOR gate 13 is L level, and NOR gate 1 is at L level.
The output of 4 is the "H1 level. At this time, the MOS transistor 11 is off and the MOS transistor 12 is on, and current flows from the first terminal N1 to the second terminal N2 through the MOS transistor 12. Conversely, First terminal N1
When the terminal N2, which is at the "L" level, is at the "H" level, the MOS transistor 11 is turned on, the MOS transistor 12 is turned off, and the voltage is changed from the second terminal N2 to the first terminal N2.
1 through the Mo8 l-transistor 11.

In this way, in this transfer gate circuit, the on/off of the two MOS transistors 11 and 12 is uniquely controlled depending on the direction of the current. In other words, Mo8
) - The current direction of each of the transistors 11 and 12 is always constant. Therefore, in these MOS transistors,
Unlike conventional transfer gates, the source and drain do not operate in reverse, making them less susceptible to deterioration caused by hot carrier effects.

FIG. 2 shows a transfer gate circuit of another embodiment.

This example utilizes an 0MO3 structure. That is, of the two MOS transistors 21 and 22 forming the main part of the transfer gate, the former is an n-channel, and the latter is an n-channel. The sources of these MOS transistors 21 and 22,
One of the trains is commonly connected to the second terminal N2, and the gates are controlled by clocks φ and φ, respectively. Further, the other of the source and drain of each MOS transistor 21.22 is connected to the first terminal N1 via MOS transistors 23.24 having the same conductive channel.

These MOS transistors 23 and 24 are control gates that specify the current path, and their gates are also connected to the first terminal Nl.
It is connected to the.

The first terminal N1 is “H” level and the second terminal N2 is “L”
Tl level and clock φ is °゛H″H″ level MO
Both the S transistors 21 and 22 are on, and as a result, the ``L'' level potential of the terminal N2 of the box 2 is transmitted to one end of the Mo8I transistor 23, 24, so the MOS transistor 23 is on and the MOS transistor 24 is off. Become. Therefore, Mo8 is transferred from the first terminal N1 to the second terminal N2.
Current flows through the t-transistor 23.21. 1st
H1 level of terminal N1 and second terminal N2 of 11 L
When the Tl level is reversed, the MOS transistor 23 is turned off and the Mo8 transistor 24 is turned on, contrary to the above.
Current from the second terminal N2 to the first terminal N1 flows through the MOS transistors 22,24.

Therefore, this embodiment also provides the same effects as the previous embodiment.

FIG. 3 shows another embodiment using only n-channel MOS transistors. MOS transistors 31.3'2 constituting the main part of the transfer gate are connected in series between the first terminal Nl and the second terminal N2 via Mo8 l-transistors 33.34 as control gates. ing. The gate of the Mo8 t-transistor 33 is directly controlled by the first terminal N1, and the gate of the MOS transistor 34
The gate of is controlled by the potential obtained by inverting the potential of the first terminal N by an inverter 35.

The operation of this transfer gate circuit is substantially similar to that of the circuit of FIG. When the clock signal φ is at the iiHO level, both MOS transistors 31 and 32 are on, but the first terminal N! is “H” level, second terminal N2
If is 'L' level, then Mo8 l-transistor 33
is on, and the MOS transistor 34 is off. Therefore, at this time, the current from the first terminal N1 to the second terminal N2 flows through the MOS transistors 33 and 31. ``H'' level of the first terminal N1 and second terminal N2, ``L Tl
If the levels are opposite, the second terminal N2 to the first terminal N1
The current flows through the MOS transistors 32 and 34.

In this manner, also in this embodiment, since the direction of the current in the Mo8 l-transistor constituting the transfer gate is specified, the same effects as in the previous embodiment can be obtained.

FIG. 4 shows an embodiment in which only the current direction of the MOS transistor 41 of the two n-channel Mo8 transistors 41 and 42 forming the transfer gate is specified. For this purpose, an n-channel MOS transistor 43 as an IIjt[l gate is provided only on the MOS transistor 41 side.

In this transfer gate, the first terminal N1 is “H”
When the "H" level terminal N2 is at the 11L Tl level and the clock signal φ is at the "H" level, all MOS transistors 41. j2.43 is on. At this time, the current flowing from the first terminal N1 to the second terminal N2 is Mo8 t-
It passes through both transistors 41 and 42. '1st terminal N1
is at the 111'l+ level and the second terminal N2 is at the "HTl level," the MOS transistor 43 is turned off, and the second
The current from the terminal N2 to the first terminal N1 flows through the MOS transistor 42 side.

In this embodiment, since the current direction is specified for the M, 08l-transistor 41, the influence of characteristic deterioration is small as in the previous embodiment. Although the current direction of the MOS transistor 42 is not specified, the first terminal N! is 11
In the mode where the second terminal N2 is at L level, current flows through both MOS transistors 41 and 42, so the degree of characteristic deterioration due to hot carriers is small to begin with, and therefore the source and drain can be used with the source and drain reversed. The impact of this is also small.

The present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, the reliability of the transfer gate circuit can be improved by specifying the current direction of the two Mo8 t-transistors constituting the current path. The lifespan of various integrated circuits can be extended.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a transfer gate circuit of one embodiment of the present invention, FIG. 2 is a diagram showing a transfer gate circuit of another embodiment, and FIG. 3 is a diagram showing a transfer gate circuit of still another embodiment. , FIG. 4 is a diagram showing a transfer gate circuit of still another embodiment, and FIG. 5 is a diagram showing static characteristics of a MOS transistor to explain the problems of the conventional transfer gate circuit. N1...first terminal, N2...second terminal, φ, φ・
...Clock signal, 11.12...n channel MOS
Transistor, 1.3.14...Nor gate, 21.
...n-channel MOS transistor, 22...p-F
- Janel MO8i- transistor, 23...n channel MOS transistor, 24... n channel Mo8 transistor, 31.32... n channel Mo8 l-
transistor, 33.34...n channel MOS transistor, 35...inverter, 41.42...n channel MOS transistor, 43...n channel Mo
8 l-transistor. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure l Figure 3 Figure 4 os Figure 5

Claims (5)

[Claims] (1) A transfer gate circuit characterized by having two MOS transistors arranged side by side that are controlled by a clock signal and a control gate that specifies the current direction of at least one of these MOS transistors. (2) The transfer gate circuit according to claim 1, wherein the two MOS transistors are MOS transistors having the same conductive channel. (3) The transfer gate circuit according to claim 1, wherein the two MOS transistors are MOS transistors with different conduction channels. (4) The control gate circuit controls the two MOs according to the “H” level and “L” level of one of the data input/output terminals.
2. The transfer gate circuit according to claim 1, which controls on/off the S transistor. (5) The control gate circuit has a MOS transistor that is connected in series to each of the two MOS transistors and is controlled to be turned on or off according to the "H" level or "L" level of the data input/output terminal. A transfer gate circuit according to claim 1.